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1. 发明授权

US08560797B2 Method and apparatus for indicating mask information 有权
标题翻译：用于指示掩模信息的方法和装置
公开(公告)号：US08560797B2
公开(公告)日：2013-10-15
申请号：US13421701
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasborro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasborro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括一个接口，用于在第一组多条引线上向DRAM发送一个第一代码，以指示第一个数据要写入DRAM，列地址以指示要写入第一数据的DRAM中的存储器核的列位置。该接口还用于发送第二代码以指示是否将第一数据的掩码信息发送到DRAM。如果第二代码指示将发送掩码信息，则在发送第二代码之后发送列地址的一部分和掩码信息的一部分。接口进一步通过与第一多个电线分开的第二多个电线将DRAM发送到第一数据。

2. 发明申请

US20120173811A1 Method and Apparatus for Delaying Write Operations 审中-公开
标题翻译：延迟写入操作的方法和装置
公开(公告)号：US20120173811A1
公开(公告)日：2012-07-05
申请号：US13421753
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括用于向DRAM发送第一代码以指示要将第一数据写入DRAM的接口。第一代码将由DRAM采样并由DRAM在DRAM发出之前的第一时间段内保持。该接口在从DRAM的第一代码被采样起经过了第二时间段之后，进一步发送由DRAM采样的第一数据。该接口还用于发送与第一代码不同的第二代码，以指示要从DRAM读取第二数据。第二个代码由外部时钟信号的一个或多个边缘上的DRAM采样。

3. 发明授权

US08019958B2 Memory write signaling and methods thereof 有权
标题翻译：存储器写入信令及其方法
公开(公告)号：US08019958B2
公开(公告)日：2011-09-13
申请号：US12875483
申请日：2010-09-03
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarre , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarre , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.
摘要翻译：在控制存储器件的方法中，以下是通过第一组互连资源传送的：指定一行存储器单元的激活的第一命令; 指定写操作的第二命令，其中写数据被写入行; 指定在写入数据写入之后是否发生预充电的一点; 以及指定是否将为写入操作发布数据掩码信息的代码。如果代码指定信息将被发出，则在传送代码之后，通过第一组互连资源传送指定是否选择性地写入写入数据的部分的信息。要写入与写入操作相关的写入数据通过与第一组互连资源分开的第二组互连资源传送。

4. 发明授权

US07870357B2 Memory system and method for two step memory write operations 有权
标题翻译：用于两步存储器写操作的存储器系统和方法
公开(公告)号：US07870357B2
公开(公告)日：2011-01-11
申请号：US12242870
申请日：2008-09-30
申请人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
发明人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
IPC分类号： G06F12/00
CPC分类号： G11C7/1039 , G06F13/1626 , G11C7/1006 , G11C7/22 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.
摘要翻译：一种操作包括存储器核心的存储器组件的方法，包括从外部控制线接收指定写入操作的写入命令。写命令在接收到写命令后第一个时间段被存储。在第一时间段之后，响应写入命令启动写入操作。在写入操作期间，接收数据的未屏蔽部分被写入存储器核心，其中数据的未屏蔽部分是由接收到的掩码信息识别为不被掩蔽的数据的位。

5. 发明授权

US07581121B2 System for a memory device having a power down mode and method 有权
标题翻译：具有断电模式和方法的存储器件的系统
公开(公告)号：US07581121B2
公开(公告)日：2009-08-25
申请号：US11151791
申请日：2005-06-14
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F1/00 , G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.
摘要翻译：一种系统，包括存储位置以存储表示随机存取存储器件的定时参数的信息。集成电路装置生成代表在从断电模式退出的随机存取存储装置与随机存取存储装置能够接收指令的时间之间经过的时间段的值。集成电路装置根据表示随机存取存储装置的定时参数的信息生成该值。

6. 发明授权

US07496709B2 Integrated circuit memory device having delayed write timing based on read response time 有权
标题翻译：具有基于读取响应时间的延迟写入定时的集成电路存储器件
公开(公告)号：US07496709B2
公开(公告)日：2009-02-24
申请号：US11953803
申请日：2007-12-10
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.
摘要翻译：集成电路存储器件包括用于存储写入数据的存储器核心，用于接收写入数据的第一组互连资源以及用于接收与写入数据相关联的写入命令的第二组互连资源。指示掩码信息是否包括在写入命令中的信息，其中当包括在写入命令中时，掩码信息指定是否选择性地将写入数据的部分写入存储器核心。

7. 发明授权

US07360050B2 Integrated circuit memory device having delayed write capability 失效
标题翻译：具有延迟写入能力的集成电路存储器件
公开(公告)号：US07360050B2
公开(公告)日：2008-04-15
申请号：US11681375
申请日：2007-03-02
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.
摘要翻译：集成电路存储器件具有第一组引脚，以使用时钟信号接收行地址，后跟列地址。器件具有第二组引脚，用于使用时钟信号接收检测命令和写入命令。 sense命令指定设备激活由行地址标识的一行存储器单元。 write命令指定存储器件接收写入数据，并将写入数据存储在由列地址标识的存储单元行中的位置。在从第二组引脚接收写入命令的第一时间段开始第一个延迟之后，将写入命令内部发布到存储器件。在从第一时间段开始第二延迟之后，在第三组引脚处接收写入数据。

8. 发明授权

US06347354B1 Apparatus and method for maximizing information transfers over limited interconnect resources 失效
标题翻译：在有限互连资源上最大化信息传输的装置和方法
公开(公告)号：US06347354B1
公开(公告)日：2002-02-12
申请号：US09169748
申请日：1998-10-09
申请人： Abhijit M. Abhyankar , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis
发明人： Abhijit M. Abhyankar , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to the problem of packing all of the required information including data, control and address information over a limited number of interconnect lines in an optimized fashion. In one embodiment, the present invention combines different control information, such as row address and bank address information into a unified address field wherein one or more bits can be shared. By sharing bits across various address fields, the present invention conserves bandwidth that is required by the control signals. In another embodiment, the present invention provides various schemes for defining and constructing packets of information that maximize the amount of information carried by a given packet across a limited number of interconnect lines.
摘要翻译：本发明提供了用于在涉及存储器件的电子系统中优化信息传输的各种技术，以提高数据带宽。本发明提供了解决方案，以优化的方式在有限数量的互连线上打包所有所需信息，包括数据，控制和地址信息。在一个实施例中，本发明将不同的控制信息（诸如行地址和存储体地址信息）组合成可以共享一个或多个位的统一地址字段。通过在各种地址字段中共享位，本发明节省了控制信号所需的带宽。在另一个实施例中，本发明提供了用于定义和构造信息分组的各种方案，其使得跨越有限数量的互连线路的给定分组携带的信息量最大化。

9. 发明申请

US20120173810A1 Method and Apparatus for Indicating Mask Information 有权
标题翻译：用于指示面罩信息的方法和装置
公开(公告)号：US20120173810A1
公开(公告)日：2012-07-05
申请号：US13421701
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括一个接口，用于在第一组多条引线上向DRAM发送一个第一代码，以指示第一个数据要写入DRAM，列地址以指示要写入第一数据的DRAM中的存储器核的列位置。该接口还用于发送第二代码以指示是否将第一数据的掩码信息发送到DRAM。如果第二代码指示将发送掩码信息，则在发送第二代码之后发送列地址的一部分和掩码信息的一部分。接口进一步通过与第一多个电线分开的第二多个电线将DRAM发送到第一数据。

10. 发明申请

US20110093669A1 Memory System and Method for Two Step Memory Write Operations 有权
标题翻译：用于两步存储器写入操作的存储器系统和方法
公开(公告)号：US20110093669A1
公开(公告)日：2011-04-21
申请号：US12975316
申请日：2010-12-21
申请人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
发明人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
IPC分类号： G06F12/00
CPC分类号： G11C7/1039 , G06F13/1626 , G11C7/1006 , G11C7/22 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.
摘要翻译：一种操作包括存储器核心的存储器组件的方法，包括从外部控制线接收指定写入操作的写入命令。写命令在接收到写命令后第一个时间段被存储。在第一时间段之后，响应写入命令启动写入操作。在写入操作期间，接收数据的未屏蔽部分被写入存储器核心，其中数据的未屏蔽部分是由接收到的掩码信息识别为不被掩蔽的数据的位。

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