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    • 2. 发明授权
    • Granularity memory column access
    • 粒度内存列访问
    • US06825841B2
    • 2004-11-30
    • US09949464
    • 2001-09-07
    • Craig E. HampelRichard E. WarmkeFrederick A. Ware
    • Craig E. HampelRichard E. WarmkeFrederick A. Ware
    • G06F1576
    • G09G5/39G09G5/393G09G2360/122
    • A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially different column addresses depending on the needs of the device utilizing the memory. For example, the column addresses might be based on a received CAS address and an accompanying offset. This allows data access at alignments that do not necessarily correspond to CAS alignments. The technique is utilized in conjunction with graphics systems in which tiling is used. In systems such as this, memory offsets are specified in terms of pixel columns and rows. The technique is also used in conjunction with a router such as a TCP/IP router, in which individual packets are aligned at CAS boundaries. In this situation, the decoder logic is alternatively configurable to allow access of either an information packet or a plurality of packet headers during a single memory access cycle.
    • 存储器件包括多个数据I / O通道和相应的通道或列解码器。 代替向每个列解码器提供相同的地址,解码器逻辑根据使用存储器的设备的需要来计算潜在的不同的列地址。 例如,列地址可能基于接收的CAS地址和附带的偏移。 这允许在不一定对应于CAS对准的对准处的数据访问。 该技术与使用平铺的图形系统结合使用。 在这样的系统中,以像素列和行来指定存储器偏移。 该技术还与诸如TCP / IP路由器的路由器结合使用,其中各个分组在CAS边界处对齐。 在这种情况下,解码器逻辑可选地可配置为允许在单个存储器访问周期期间访问信息分组或多个分组报头。
    • 9. 发明授权
    • Methods and arrangements for conditionally enforcing CAS latencies in memory devices
    • 有条件地执行存储器件中CAS延迟的方法和安排
    • US06542416B1
    • 2003-04-01
    • US10001030
    • 2001-11-02
    • Craig E. HampelFrederick A. WareRichard E. Warmke
    • Craig E. HampelFrederick A. WareRichard E. Warmke
    • G11C700
    • G11C11/4076G11C7/1072G11C7/22G11C2207/2281G11C2207/229
    • Methods and arrangements are provided for use in memory devices, which allow column address strobe (CAS) timing to adjust to, and/or be adjusted by a controller to, have both minimal unloaded latency and optimal pipelined latency. A delay CAS (DC) period is only applied until a row-to-column delay (tRCD) has been satisfied. Once the tRCD has been satisfied, then the DC period is not enforced for subsequent CAS operations within the memory core associated with a page hit. When a subsequent read command is received at the input/output pins of the memory device and a corresponding RAS operation is performed in the memory core, then the tRCD will again need to be satisfied and a DC period will again be enforced. Consequently the methods and arrangements allow the CAS delay to be dynamically and selectively adjusted to best support the workload. This results in better performance and increased bandwidth.
    • 方法和布置被提供用于存储器件,其允许列地址选通(CAS)时序调整到和/或被控制器调整为具有最小的无负载延迟和最佳流水线延迟。 只有在满足行到列延迟(tRCD)之后才应用延迟CAS(DC)周期。 一旦满足tRCD,则在与页面匹配相关联的存储器核心内的后续CAS操作中不执行DC周期。 当在存储器件的输入/输出引脚处接收到随后的读取命令并且在存储器核心中执行相应的RAS操作时,则再次需要满足tRCD并且再次执行DC周期。 因此,方法和布置允许CAS延迟被动态和选择性地调整以最好地支持工作负载。 这导致更好的性能和增加的带宽。