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71. 发明申请

US20110078432A1 RETRIEVING BOOT INSTRUCTIONS FROM NONVOLATILE MEMORY 有权
标题翻译：从非易失性存储器中检索引导指令
公开(公告)号：US20110078432A1
公开(公告)日：2011-03-31
申请号：US12961449
申请日：2010-12-06
申请人： Stephen Wu
发明人： Stephen Wu
IPC分类号： G06F9/00 , G06F1/24
CPC分类号： G06F9/4406 , G06F1/24 , G06F9/4401 , G06F9/4403 , G06F9/44573 , G06F12/0246 , G06F2212/7201
摘要： Systems and processes for booting a device can be implemented by detecting a reset signal associated with the device and retrieving a predetermined page of data from a nonvolatile memory location into a register associated with the nonvolatile memory. The nonvolatile memory may be designed and implemented such that each page of data is retrieved from the nonvolatile memory as a unit, and the page of data includes instructions for use in booting the device. A command to read data stored in the register is received, and the command can include an address identifying a location of one or more instructions within the register. In response, the one or more instructions are retrieved from the register for execution by a processor.
摘要翻译：用于引导设备的系统和过程可以通过检测与设备相关联的复位信号并从非易失性存储器位置检索数据到与非易失性存储器相关联的寄存器中来实现。可以设计和实现非易失性存储器，使得每个数据页作为一个单元从非易失性存储器检索，并且数据页包括用于引导设备的指令。接收读取存储在寄存器中的数据的命令，并且该命令可以包括标识寄存器内的一个或多个指令的位置的地址。作为响应，从寄存器检索一个或多个指令以由处理器执行。

72. 发明申请

US20100201451A1 METHOD AND SYSTEM FOR FREQUENCY CALIBRATION OF A VOLTAGE CONTROLLED RING OSCILLATOR 审中-公开
标题翻译：电压控制振荡器频率校准的方法和系统
公开(公告)号：US20100201451A1
公开(公告)日：2010-08-12
申请号：US12367280
申请日：2009-02-06
申请人： Stephen Wu
发明人： Stephen Wu
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L2207/06
摘要： Aspects of a method and system for frequency calibration of a voltage controlled ring oscillator are provided. In this regard, an oscillating voltage may be generated via a voltage controlled ring oscillator comprising a plurality of delay cells. Each of the plurality of delay cells may comprise a MOSFET differential pair coupled to a plurality of variable resistors. A frequency of oscillation and amplitude of the generated oscillating voltage may be controlled by controlling a resistance of the plurality of variable resistors. The frequency of oscillation and amplitude may be controlled via one or more digital control words generated by a baseband processor, a DSP, and/or a memory. The digital control words may comprise a control word for finely tuning the frequency of oscillation and amplitude and a control word for coarsely tuning the frequency of oscillation and amplitude.
摘要翻译：提供了一种用于压控环形振荡器的频率校准的方法和系统。在这方面，可以经由包括多个延迟单元的压控环形振荡器产生振荡电压。多个延迟单元中的每一个可以包括耦合到多个可变电阻器的MOSFET差分对。可以通过控制多个可变电阻器的电阻来控制产生的振荡电压的振荡频率和振幅。可以通过由基带处理器，DSP和/或存储器产生的一个或多个数字控制字来控制振荡频率和振幅。数字控制字可以包括用于微调振荡频率和幅度的控制字和用于粗调谐振荡频率的控制字。

73. 发明申请

US20100155887A1 Common plate capacitor array connections, and processes of making same 有权
标题翻译：普通板电容阵列连接及其制作工艺
公开(公告)号：US20100155887A1
公开(公告)日：2010-06-24
申请号：US12317656
申请日：2008-12-22
申请人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
发明人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/101 , H01L28/90
摘要： A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.
摘要翻译：形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。该过程包括将电容器单元边界的第一高度降低到第二高度。普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。

74. 发明授权

US07682842B2 Method of adaptively selecting chips for reducing in-line testing in a semiconductor manufacturing line 失效
标题翻译：自适应选择芯片以减少半导体生产线中的在线测试的方法
公开(公告)号：US07682842B2
公开(公告)日：2010-03-23
申请号：US12129712
申请日：2008-05-30
申请人： Rao H. Desineni , Xu Ouyang , Hargurpreet Singh , Yunsheng Song , Stephen Wu
发明人： Rao H. Desineni , Xu Ouyang , Hargurpreet Singh , Yunsheng Song , Stephen Wu
IPC分类号： H01L21/00
CPC分类号： G01R31/2894
摘要： A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.
摘要翻译：一种用于识别潜在有缺陷的集成电路芯片的方法，并将其从将来的测试中排除，因为晶片移动通过生产线。该方法包括数据收集步骤，基于当晶片向下移动时收集的信息将标记为潜在的坏芯片的晶片上的芯片标记通过消除对标记芯片的任何进一步测试，优选使用测试成本数据库来评估测试成本节省。考虑到将要执行的所有将来的测试，如果确定测试成本节省是重要的，则标记的芯片被跳过。标记坏芯片是基于各种标准和模型，通过对标记芯片的样品进行晶圆最终测试并反馈最终测试结果来动态调整。动态自适应调整方法优选地包括反馈循环或迭代过程，以在评估补救筹码的利润与额外的测试成本时评估金融权衡。

75. 发明授权

US07543198B2 Test data reporting and analyzing using data array and related data analysis 失效
标题翻译：使用数据阵列和相关数据分析测试数据报告和分析
公开(公告)号：US07543198B2
公开(公告)日：2009-06-02
申请号：US11163527
申请日：2005-10-21
申请人： William J. Ferrante , John J. Cassels , Stephen Wu
发明人： William J. Ferrante , John J. Cassels , Stephen Wu
IPC分类号： G06F11/00 , G11C29/00 , G01R31/28 , G01R31/02 , G01R31/26
CPC分类号： G11C29/56 , G01R31/31935 , G11C29/56008 , G11C2029/5604
摘要： Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array. One method includes obtaining the test data, and reporting the test data in a data array, which includes at least two portions representing different tests. Data stored in the data array is organized according to a translation table, which describes the locations of data for tests and criteria for data to be analyzed within the data array. Numerous other data arrangements such as a coordinate file listing a pre-defined maximum number of fail points, or a chip report including fail points by chip may also be generated. The data array reports all test data in a more easily generated and stored form, and may be converted to an image. A data analysis method for analyzing data using the data array is also presented.
摘要翻译：使用数据阵列从阵列结构的多个测试报告和/或分析测试数据。一种方法包括获得测试数据，并将测试数据报告在数据阵列中，该数据阵列包括表示不同测试的至少两个部分。存储在数据阵列中的数据根据翻译表进行组织，该转换表描述了要在数据阵列中分析的数据的测试数据和标准的位置。也可以生成诸如列出预定义的最大失败点数的坐标文件或包括芯片故障点的芯片报告的许多其他数据布置。数据阵列以更容易生成和存储的形式报告所有测试数据，并可将其转换为图像。还提出了一种用于使用数据阵列分析数据的数据分析方法。

76. 发明申请

US20090128225A1 STRUCTURE OF AN APPARATUS FOR PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE SEMICONDUCTOR FUSE 失效
标题翻译：用于编程电子可编程半导体熔丝器的设备结构
公开(公告)号：US20090128225A1
公开(公告)日：2009-05-21
申请号：US11941308
申请日：2007-11-16
申请人： Dan Moy , Stephen Wu , Peter Wang , Brian W. Messenger , Edwin Soler , Gabriel Chiulli
发明人： Dan Moy , Stephen Wu , Peter Wang , Brian W. Messenger , Edwin Soler , Gabriel Chiulli
IPC分类号： H01H37/76
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.
摘要翻译：一种用于编程电子可编程半导体保险丝的装置的设计结构。该装置将编程电流作为一系列多个脉冲施加到熔丝链路。将编程电流应用为一系列多个短脉冲提供足够高的编程电流电平，以确保可靠且有效的电迁移，同时避免超过熔丝链的温度限制。

77. 发明申请

US20080231375A1 METHOD AND SYSTEM FOR USING A FREQUENCY LOCKED LOOP LOGEN IN OSCILLATOR SYSTEMS 有权
标题翻译：在振荡器系统中使用频率锁定环路的方法和系统
公开(公告)号：US20080231375A1
公开(公告)日：2008-09-25
申请号：US11831399
申请日：2007-07-31
申请人： Jared Welz , Brima Babatunde Ibrahim , Stephen Wu
发明人： Jared Welz , Brima Babatunde Ibrahim , Stephen Wu
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , H03L7/181
摘要： Aspects of a method and system for using a frequency locked loop LOGEN in oscillator systems may include generating an oscillating signal via one or more circuits comprising a feedback loop. The generation may be controlled by enabling or disabling the feedback loop, based on the generated oscillating signal. The one or more circuits may comprise a frequency-locked loop (FLL) that may enable the generation of the oscillating signal. The frequency-locked loop may comprise a voltage-controlled oscillator. The feedback loop may be disabled when an estimated frequency difference between a reference signal and a feedback signal may be less than or equal to a specified threshold. The feedback loop may be enabled when an estimated frequency difference between a reference signal and a feedback signal may be greater than a particular threshold.
摘要翻译：在振荡器系统中使用频率锁定环路LOGEN的方法和系统的方面可以包括经由包括反馈回路的一个或多个电路产生振荡信号。可以基于产生的振荡信号来启用或禁用反馈回路来控制一代。一个或多个电路可以包括可以产生振荡信号的频率锁定环（FLL）。频率锁定环路可以包括压控振荡器。当参考信号和反馈信号之间的估计频率差可以小于或等于指定阈值时，可以禁用反馈环路。当参考信号和反馈信号之间的估计频率差可能大于特定阈值时，可以使能反馈回路。

78. 发明申请

US20080211590A1 METHOD AND SYSTEM FOR A VARACTOR-TUNED VOLTAGE-CONTROLLED RING OSCILLATOR WITH FREQUENCY AND AMPLITUDE CALIBRATION 审中-公开
标题翻译：用于具有频率和幅度校准的变量调制电压控制振荡器的方法和系统
公开(公告)号：US20080211590A1
公开(公告)日：2008-09-04
申请号：US11680883
申请日：2007-03-01
申请人： Stephen Wu
发明人： Stephen Wu
IPC分类号： H03K3/02
CPC分类号： H03K3/0322
摘要： Aspects of a method and system for a varactor-tuned voltage-controlled ring oscillator with frequency and amplitude calibration may include generating in a voltage controlled ring oscillator, an oscillating signal using delay cells, wherein each delay cell may comprise varactors and variable resistors. The frequency of the generated oscillating signal may be variable and may be calibrated by calibrating a delay associated with the delay cells. The amplitude of the generated oscillating signal may be calibrated by adjusting variable resistors and current sources within the delay cells. The frequency of the generated oscillating signal may be varied by varying the delay of at least one delay cell through changing the capacitance of its varactors. Changing a control voltage may change the varactor capacitance. The gain of the ring oscillator may be reduced by adjusting the varactors, and the generated oscillating signal may be a square wave signal.
摘要翻译：用于具有频率和幅度校准的变容二极管调谐电压控制环形振荡器的方法和系统的方面可以包括在压控环形振荡器中产生使用延迟单元的振荡信号，其中每个延迟单元可以包括变容二极管和可变电阻器。产生的振荡信号的频率可以是可变的，并且可以通过校准与延迟单元相关联的延迟来校准。可以通过调节延迟单元内的可变电阻器和电流源来校准产生的振荡信号的振幅。所产生的振荡信号的频率可以通过改变其变容二极管的电容来改变至少一个延迟单元的延迟来改变。改变控制电压可能会改变变容二极管电容。可以通过调节变容二极管来减小环形振荡器的增益，并且所产生的振荡信号可以是方波信号。

79. 发明申请

US20070012982A1 Multipurpose metal fill 审中-公开
标题翻译：多功能金属填充
公开(公告)号：US20070012982A1
公开(公告)日：2007-01-18
申请号：US11526790
申请日：2006-09-25
申请人： Stephen Wu , Ernie Geronaga
发明人： Stephen Wu , Ernie Geronaga
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured as a capacitor is formed within each of the n-well regions and is coupled between supply and circuit common to filter supply noise. A metal layer capacitor is formed above each MOSFET capacitor and is coupled between supply and circuit common. The present inventive circuit adds metallization to satisfy metal percentage requirements and to improve noise filtering. Each barrier region includes a plurality of coupled (shorted) n-wells with MOSFET transistors configured as capacitors. Additionally, in the described embodiment, the metallization layer is formed to create metal capacitors on top layers of the n-well regions to create additional noise filtering between supply and ground.
摘要翻译：本发明增加了用于降低衬底噪声的多个衬底屏障。在模拟和数字部分之间以及在敏感的模拟电路的至少一侧上形成由p型衬底内形成的多个相同大小的n阱区组成的势垒。配置为电容器的MOSFET晶体管形成在每个n阱区域中，并且耦合在电源和电路之间，以滤除电源噪声。在每个MOSFET电容器上方形成一个金属层电容器，并在电源和电路之间耦合。本发明的电路增加了金属化以满足金属百分比要求并改善噪声过滤。每个屏障区域包括多个被配置为电容器的MOSFET晶体管的耦合（短路）n阱。另外，在所描述的实施例中，形成金属化层以在n阱区域的顶层上形成金属电容器，以在电源和地之间产生额外的噪声滤波。

80. 发明授权

US07088962B2 On-chip loop filter for a PLL 有权
标题翻译： PLL的片上环路滤波器
公开(公告)号：US07088962B2
公开(公告)日：2006-08-08
申请号：US10727371
申请日：2003-12-04
申请人： Seema B. Anand , Stephen Wu
发明人： Seema B. Anand , Stephen Wu
IPC分类号： H04B1/40 , H04B1/06 , H04B7/00
CPC分类号： H03L7/093 , H03L7/0891
摘要： An on-chip loop filter includes a 1st resistor, a 1st capacitor, a 2nd capacitor, a 3rd capacitor, a 2nd resistor, and a 4th capacitor. The 1st resistor is operably coupled to receive a charge pump output. The 1st capacitor is coupled in series with the 1st resistor where the second node of the 1st capacitor is coupled to a return. The 2nd capacitor is coupled in parallel with the series combination of the 1st resistor and 1st capacitor. The 3rd capacitor is coupled in parallel with the 2nd capacitor. The 2nd resistor is coupled to a node of the 3rd capacitor and to a node of the 4th capacitor. The other node of the 4th capacitor is coupled to ground. To enable these components to be placed on-chip, the 1st capacitor is of a 1st capacitor construct having a 1st quality factor, the 2nd capacitor is of a 2nd capacitor construct having a 2nd quality factor, where the 2nd quality factor is greater than the 1st quality factor, and the 3rd and 4th capacitors are of a 3rd capacitor construct having a 3rd quality factor, which is greater than the 2nd quality factor.
摘要翻译：片上环路滤波器包括1 电阻器，1 电容器，2 电容器， / SUP>电容器，2 电阻器和4 电容器。 1 电阻器可操作地耦合以接收电荷泵输出。 1 SUP电容器与1 SUP电阻器串联耦合，其中第1个电容器的第二个节点耦合到一个返回端。第二和第二电容器与第一和第二电阻器和1 SUP电容器的串联组合并联耦合。第3个电容器与第2个电容器并联耦合。 2Ω电阻器耦合到第3级电容器的节点和4Ω电容器的节点。第4个电容器的另一个节点耦合到地。为了使这些部件能够被片上放置，1 电容器是具有1＆lt; SUP＆gt;品质因子的1 电容器结构， 2 nd电容器是具有第2个质量因子的第2个电容器构造，其中第2个＆lt; 品质因子大于1＆lt; ST＆gt;品质因子，并且第3 和4 电容器为3 SUP>电容器结构，其具有大于第2个质量因子的品质因子。

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