专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US09040393B2 Method of forming semiconductor structure 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US09040393B2
公开(公告)日：2015-05-26
申请号：US13242090
申请日：2011-09-23
申请人： Liang-Gi Yao , Chia-Cheng Chen , Ta-Ming Kuan , Jeff J. Xu , Clement Hsingjen Wann
发明人： Liang-Gi Yao , Chia-Cheng Chen , Ta-Ming Kuan , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： H01L21/20 , H01L21/265 , H01L29/49 , H01L29/51 , H01L21/28 , H01L29/66 , H01L29/78
CPC分类号： H01L21/02661 , H01L21/26506 , H01L21/28088 , H01L21/28194 , H01L21/2822 , H01L21/823418 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate.
摘要翻译：形成半导体器件的方法包括化学清洗衬底的表面以在表面上形成化学氧化物材料。化学氧化物材料的至少一部分以约2纳米/分钟（nm / min）或更小的去除速率除去。此后，在衬底的表面上形成栅极电介质层。

72. 发明授权

US08963257B2 Fin field effect transistors and methods for fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US08963257B2
公开(公告)日：2015-02-24
申请号：US13293732
申请日：2011-11-10
申请人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yi-Tang Lin , Chih-Sheng Chang
发明人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yi-Tang Lin , Chih-Sheng Chang
IPC分类号： H01L27/088 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/66
CPC分类号： H01L29/66818 , H01L21/2236 , H01L21/823431 , H01L21/823462 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823857 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.
摘要翻译：本发明涉及Fin场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括顶表面的衬底; 在所述基板顶表面上方延伸的第一翅片和第二翅片，其中每个翼片具有顶表面和侧壁; 所述第一和第二翅片之间的绝缘层从所述基板顶表面向上延伸所述翅片; 覆盖第一鳍片的顶表面和第一鳍片的侧壁的第一栅极电介质和覆盖第二鳍片的顶表面和第二鳍片的侧壁的第二栅极电介质具有小于第一厚度的第二厚度; 以及穿过第一栅极电介质和第二栅极电介质两端的导电栅极条。

73. 发明授权

US08816444B2 System and methods for converting planar design to FinFET design 有权
公开(公告)号：US08816444B2
公开(公告)日：2014-08-26
申请号：US13416862
申请日：2012-03-09
申请人： Clement Hsingjen Wann , Chih-Sheng Chang , Yi-Tang Lin , Ming-Feng Shieh , Ting-Chu Ko , Chung-Hsien Chen
发明人： Clement Hsingjen Wann , Chih-Sheng Chang , Yi-Tang Lin , Ming-Feng Shieh , Ting-Chu Ko , Chung-Hsien Chen
IPC分类号： H01L27/088
CPC分类号： H01L27/0886 , G03F1/00 , G06F17/5068 , G06F17/5081 , H01L21/823821 , H01L21/845 , H01L23/48 , H01L27/0207 , H01L29/41791 , H01L29/66795 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

74. 发明申请

US20130075833A1 MULTI-LAYER SCAVENGING METAL GATE STACK FOR ULTRA-THIN INTERFACIAL DIELCTRIC LAYER 有权
标题翻译：用于超薄界面层压层的多层金属栅极叠层
公开(公告)号：US20130075833A1
公开(公告)日：2013-03-28
申请号：US13239804
申请日：2011-09-22
申请人： Kuan-Ting Liu , Liang-Gi Yao , Yasutoshi Okuno , Clement Hsingjen Wann
发明人： Kuan-Ting Liu , Liang-Gi Yao , Yasutoshi Okuno , Clement Hsingjen Wann
IPC分类号： H01L29/772
CPC分类号： H01L21/823842 , H01L21/28008 , H01L21/28079 , H01L21/28088 , H01L27/092 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer.
摘要翻译：公开了一种多层扫气金属栅叠层及其制造方法。在一个示例中，设置在半导体衬底上的栅极堆叠包括设置在半导体衬底上的界面电介质层，设置在界面电介质层上的高k电介质层，设置在高k电介质层上的第一导电层，以及设置在所述第一导电层上的第二导电层。第一导电层包括设置在高k电介质层上的第一金属层，设置在第一金属层上的第二金属层和设置在第二金属层上的第三金属层。第一金属层包括从界面电介质层清除氧杂质的材料，第二金属层包括从第三金属层吸附氧杂质并防止氧杂质扩散到第一金属层中的材料。

75. 发明申请

US20130043512A1 Semiconductor Device Manufacturing Methods and Methods of Forming Insulating Material Layers 有权
公开(公告)号：US20130043512A1
公开(公告)日：2013-02-21
申请号：US13212834
申请日：2011-08-18
申请人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L21/31 , H01L21/28 , H01L29/78
CPC分类号： H01L21/02274 , H01L21/02164 , H01L21/022 , H01L21/0228 , H01L21/02332 , H01L21/324 , H01L29/66795
摘要： Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

76. 发明授权

US08264021B2 Finfets and methods for forming the same 有权
标题翻译： Finfets及其形成方法
公开(公告)号：US08264021B2
公开(公告)日：2012-09-11
申请号：US12761686
申请日：2010-04-16
申请人： Li-Shyue Lai , Tsz-Mei Kwok , Chih Chieh Yeh , Clement Hsingjen Wann
发明人： Li-Shyue Lai , Tsz-Mei Kwok , Chih Chieh Yeh , Clement Hsingjen Wann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure.
摘要翻译： Fin场效应晶体管（FinFET）包括在衬底上的鳍状沟道体。栅电极设置在翅片通道体的上方。至少一个源极/漏极（S / D）区域邻近鳍状物通道本体设置。所述至少一个S / D区域基本上不包括任何鳍结构。

77. 发明授权

US08048795B2 Self-assembly pattern for semiconductor integrated circuit 有权
标题翻译：半导体集成电路的自组装模式
公开(公告)号：US08048795B2
公开(公告)日：2011-11-01
申请号：US12610282
申请日：2009-10-31
申请人： Tsung-Lin Lee , Clement Hsingjen Wann , Ching-Yu Chang
发明人： Tsung-Lin Lee , Clement Hsingjen Wann , Ching-Yu Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.
摘要翻译：提供一种制造半导体器件的方法，其包括提供衬底。材料层形成在衬底上。聚合物层形成在材料层上。使用聚合物层的一部分自组装纳米尺寸的特征。使用纳米尺寸的特征对衬底进行图案化。

78. 发明授权

US07862962B2 Integrated circuit layout design 有权
标题翻译：集成电路布局设计
公开(公告)号：US07862962B2
公开(公告)日：2011-01-04
申请号：US12356405
申请日：2009-01-20
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.
摘要翻译：提供了一种包括集成电路的布局设计的方法。提供了第一种模式。第一图案包括虚线特征的阵列和与虚线特征相邻的多个间隔元件。提供了第二种模式。第二图案定义了集成电路器件的有源区。确定有源区的边缘间隔元件。假线特征阵列的虚线特征被偏置（例如，宽度增加），虚线特征与边缘间隔元件相邻。

79. 发明授权

US09484462B2 Fin structure of fin field effect transistor 有权
标题翻译：翅片场效应晶体管的鳍结构
公开(公告)号：US09484462B2
公开(公告)日：2016-11-01
申请号：US12766233
申请日：2010-04-23
申请人： Feng Yuan , Hung-Ming Chen , Tsung-Lin Lee , Chang-Yun Chang , Clement Hsingjen Wann
发明人： Feng Yuan , Hung-Ming Chen , Tsung-Lin Lee , Chang-Yun Chang , Clement Hsingjen Wann
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66
CPC分类号： H01L29/66795 , H01L21/308 , H01L29/7851 , H01L29/7853
摘要： An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.
摘要翻译：鳍状场效应晶体管的示例性结构包括：包括主表面的衬底; 多个翅片结构，从所述基底的主表面突出，其中每个翅片结构包括在翅片结构的侧壁与主表面成85度角的过渡位置处分离的上部和下部，其中所述上部具有基本上垂直于所述基底的主表面的侧壁和具有第一宽度的顶表面，其中所述下部具有在所述上部的相对侧上的锥形侧壁和具有第二宽度的基部宽度大于第一宽度; 以及在翅片结构之间的多个隔离结构，其中每个隔离结构从基板的主表面延伸到过渡位置上方的点。

80. 发明授权

US08799833B2 System and methods for converting planar design to FinFET design 有权
公开(公告)号：US08799833B2
公开(公告)日：2014-08-05
申请号：US13416907
申请日：2012-03-09
申请人： Clement Hsingjen Wann , Chih-Sheng Chang , Yi-Tang Lin , Ming-Feng Shieh
发明人： Clement Hsingjen Wann , Chih-Sheng Chang , Yi-Tang Lin , Ming-Feng Shieh
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式