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71. 发明申请

US20080248638A1 PROCESS FOR MANUFACTURING VOLTAGE-CONTROLLED TRANSISTOR 有权
标题翻译：制造电压控制晶体管的过程
公开(公告)号：US20080248638A1
公开(公告)日：2008-10-09
申请号：US12132605
申请日：2008-06-03
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L21/22
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/0886 , H01L29/42368 , H01L29/861
摘要： The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential.
摘要翻译：本发明提供一种利用漏极端子和辅助区域之间的寄生电阻器的自驱动LDMOS。寄生电阻形成在准连接深N型阱中的两个耗尽边界之间。当两个耗尽边界夹闭时，栅极端子处的栅极电压电位在所述漏极端子处的漏极电压电位处被钳位。由于栅极电压电位被设计为等于或高于启动阈值电压，所以LDMOS被相应地导通。此外，不需要额外的管芯空间和掩模工艺来制造寄生电阻器。此外，本发明的寄生电阻器不降低LDMOS的击穿电压和操作速度。此外，当两个耗尽边界夹断时，栅极电压电位不随着漏极 - 电压电位的增加而变化。

72. 发明申请

US20080042241A1 Voltage-controlled semiconductor structure, resistor, and manufacturing processes thereof 有权
标题翻译：电压控制半导体结构，电阻及其制造方法
公开(公告)号：US20080042241A1
公开(公告)日：2008-02-21
申请号：US11507293
申请日：2006-08-21
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/8605 , H01L29/66166
摘要： Voltage-controlled semiconductor structures, voltage-controlled resistors, and manufacturing processes are provided. The semiconductor structure comprises a substrate, a first doped well, and a second doped well. The substrate is doped with a first type of ions. The first doped well is with a second type of ions and is formed in the substrate. The second doped well is with the second type of ions and is formed in the substrate. The first type of ions and the second type of ions are complementary. A resistor is formed between the first doped well and the second doped well. A resistivity of the resistor is controlled by a differential voltage. A resistivity of the resistor relates to a first depth of the first doped well, a second depth of the second doped well, and a distance between the first doped well and the second doped well. The resistivity of the resistor is higher than that of a well resistor formed in a single doped well with the second type of ions.
摘要翻译：提供了压控半导体结构，压控电阻器和制造工艺。半导体结构包括衬底，第一掺杂阱和第二掺杂阱。衬底掺杂有第一类型的离子。第一掺杂阱具有第二类离子，并形成在衬底中。第二掺杂阱是与第二类型的离子形成在衬底中。第一类离子和第二类离子是互补的。在第一掺杂阱和第二掺杂阱之间形成电阻器。电阻的电阻率由差分电压控制。电阻器的电阻率涉及第一掺杂阱的第一深度，第二掺杂阱的第二深度以及第一掺杂阱和第二掺杂阱之间的距离。电阻器的电阻率高于在具有第二类型离子的单个掺杂阱中形成的阱电阻器的电阻率。

73. 发明授权

US06770138B2 Pattern for monitoring epitaxial layer washout 失效
标题翻译：用于监测外延层冲洗的图案
公开(公告)号：US06770138B2
公开(公告)日：2004-08-03
申请号：US10047379
申请日：2002-01-14
申请人： Shih-Feng Huang , Chih-Feng Huang , Kuo-Su Huang
发明人： Shih-Feng Huang , Chih-Feng Huang , Kuo-Su Huang
IPC分类号： C30B3500
CPC分类号： H01L23/544 , C30B33/00 , H01L2924/0002 , Y10T117/1004 , H01L2924/00
摘要： A pattern for monitoring epitaxial layer washout is disclosed. The pattern includes first and second sub-patterns. The first sub-pattern has a shape and defines one or more minimum dimensions. Obfuscation of the first sub-pattern means that epitaxial washout has occurred at least for dimensions equal to or less than the minimum dimensions. The second sub-pattern has the same shape of the first sub-pattern, but defines one or more maximum dimensions. Obfuscation of the second sub-pattern means that epitaxial washout has occurred for dimensions equal to or less than the maximum dimensions. The sub-patterns can include a pair of separated features, such as a pair of interlocking but separated L-shaped features, the separation of which defines the dimensions of the sub-patterns.
摘要翻译：公开了一种用于监测外延层冲洗的图案。该模式包括第一和第二子模式。第一子图案具有形状并且定义一个或多个最小尺寸。第一子图案的混淆意味着至少在尺寸等于或小于最小尺寸的情况下发生外延冲洗。第二子图案具有与第一子图案相同的形状，但是定义一个或多个最大尺寸。第二子图案的混淆意味着对于等于或小于最大尺寸的尺寸发生外延冲洗。子图案可以包括一对分离的特征，例如一对互锁但分开的L形特征，其分离限定子图案的尺寸。

74. 发明授权

US06475870B1 P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture 有权
标题翻译： P型LDMOS器件采用埋层解决穿孔问题及其制造工艺
公开(公告)号：US06475870B1
公开(公告)日：2002-11-05
申请号：US09910158
申请日：2001-07-23
申请人： Chih-Feng Huang , Kuo-Su Huang
发明人： Chih-Feng Huang , Kuo-Su Huang
IPC分类号： H01L21331
CPC分类号： H01L29/1083 , H01L29/42368 , H01L29/7835
摘要： P-type LDMOS devices have been difficult to integrate with N-type LDMOS devices without adding an extra mask because the former have been unable to achieve the same breakdown voltage as the latter due to early punch-through. This problem has been overcome by preceding the epitaxial deposition of N− silicon onto the P− substrate with an additional process step in which a buried N+ layer is formed at the surface of the substrate by ion implantation. This N+ buried layer significantly reduces the width of the depletion layer that extends outwards from the P− well when voltage is applied to the drain thus substantially raising the punch-through voltage.
摘要翻译： P型LDMOS器件难以与N型LDMOS器件集成而不增加额外的掩模，因为前者由于早期穿通而无法实现与后者相同的击穿电压。通过在N衬底外延沉积到P-衬底上的附加工艺步骤之前已经克服了这个问题，其中通过离子注入在衬底的表面上形成掩埋的N +层。当电压施加到漏极时，该N +掩埋层显着地减小了从P-阱向外延伸的耗尽层的宽度，从而基本上提高穿通电压。

75. 发明授权

US06348371B1 Method of forming self-aligned twin wells 有权
标题翻译：形成自对准双孔的方法
公开(公告)号：US06348371B1
公开(公告)日：2002-02-19
申请号：US09809831
申请日：2001-03-19
申请人： Chih-Feng Huang , Kuo-Su Huang , Shun-Liang Hsu
发明人： Chih-Feng Huang , Kuo-Su Huang , Shun-Liang Hsu
IPC分类号： H01L218238
CPC分类号： H01L21/823892
摘要： A process for forming self-aligned, twin well regions for a CMOS device, without the use of an oxidation retarding silicon nitride layer, has been developed. A first ion implantation procedure is used to place N type ions in a first portion of a semiconductor substrate, followed by a wet thermal oxidation procedure resulting in the growth of a thick silicon dioxide layer on the N type ions, in the first portion of the semiconductor substrate, while growing a thin silicon dioxide layer on a second portion of the lightly doped, P type semiconductor substrate. A second ion implantation procedure places P type ions through the thin silicon dioxide layer, into the second portion of the semiconductor substrate, while the thick silicon dioxide layer prevents the P type ions from reaching the first portion of the semiconductor substrate. A subsequent anneal procedure results in the formation of a N well region, in the first portion of the semiconductor substrate, self-aligned to the formed P well region, located in the second portion of the semiconductor substrate.
摘要翻译：已经开发了用于为CMOS器件形成自对准双阱区而不使用氧化阻滞氮化硅层的工艺。使用第一离子注入程序将N型离子放置在半导体衬底的第一部分中，随后进行湿热氧化过程，导致在N型离子上生长厚二氧化硅层，在第一部分半导体衬底，同时在轻掺杂的P型半导体衬底的第二部分上生长薄的二氧化硅层。第二离子注入程序使P型离子通过薄二氧化硅层进入半导体衬底的第二部分，而厚二氧化硅层防止P型离子到达半导体衬底的第一部分。随后的退火程序导致在位于半导体衬底的第二部分中的形成的P阱区自对准的半导体衬底的第一部分中的N阱区的形成。

76. 发明申请

US20120313616A1 AC DISCHARGE CIRCUIT FOR AN AC-TO-DC SWITCHING POWER CONVERTER 审中-公开
标题翻译： AC-DC-DC开关电源转换器的交流放电电路
公开(公告)号：US20120313616A1
公开(公告)日：2012-12-13
申请号：US13487049
申请日：2012-06-01
申请人： Yi-Wei Lee , Chih-Feng Huang
发明人： Yi-Wei Lee , Chih-Feng Huang
IPC分类号： G05F3/04
CPC分类号： H02M1/32 , H02M1/126 , H02M1/4258 , H02M2001/322 , Y02B70/126
摘要： An AC discharge circuit is disclosed to eliminate the need of bleeding resistors for an AC-to-DC switching power converter. The AC-to-DC switching power converter has two AC power input terminals to be connected to an AC power source, and an AC input capacitor connected between the two AC power input terminals. The AC discharge circuit has a rectifier circuit to rectify a first voltage across the AC input capacitor to be a second voltage applied to an input terminal of a JFET, and a power removal detector to monitor a third voltage at an output terminal of the JFET to trigger a power removal signal to discharge the AC input capacitor when the third voltage has been remained larger than a threshold for a de-bounce time.
摘要翻译：公开了一种AC放电电路，以消除对AC至DC开关功率转换器的出血电阻的需要。 AC-DC开关电源转换器具有两个交流电源输入端子，连接到交流电源，交流输入电容器连接在两个交流电源输入端子之间。交流放电电路具有整流电路，用于对交流输入电容器两端的第一电压进行整流，以施加到JFET的输入端上的第二电压;以及功率去除检测器，用于监测JFET输出端的第三电压当第三电压已经保持大于反跳时间的阈值时，触发掉电信号以对AC输入电容器放电。

77. 发明申请

US20120262203A1 Power supply input voltage detection circuit 失效
标题翻译：电源输入电压检测电路
公开(公告)号：US20120262203A1
公开(公告)日：2012-10-18
申请号：US13373271
申请日：2011-11-09
申请人： Hsin-Yi Wu , Chih-Feng Huang
发明人： Hsin-Yi Wu , Chih-Feng Huang
IPC分类号： H03K5/153
CPC分类号： H03K5/153
摘要： The present invention discloses a power supply input voltage detection circuit. The power supply converts an input voltage to an output voltage by a transformer which includes a primary winding and a secondary winding. The primary winding is coupled to a power switch, which receives a switching signal to adjust the output voltage. The power switch is coupled to a sensing circuit; when the power switch turns ON, the sensing circuit generates a current sense signal according to current through the primary winding. The input voltage detection circuit includes: a rising time detection circuit, which detects a period, of time during which the current sense signal rises from a low reference level to a high reference level to generate a timing signal; and a determination circuit, which generates a determination signal according to the timing signal for determining whether the input signal is a high voltage or a low voltage.
摘要翻译：本发明公开了一种电源输入电压检测电路。电源通过包括初级绕组和次级绕组的变压器将输入电压转换为输出电压。初级绕组耦合到电源开关，其接收切换信号以调节输出电压。电源开关耦合到感测电路; 当电源开关接通时，感测电路根据通过初级绕组的电流产生电流检测信号。输入电压检测电路包括：上升时间检测电路，其检测电流检测信号从低参考电平上升到高参考电平的时间段，以产生定时信号; 以及确定电路，其根据用于确定输入信号是高电压还是低电压的定时信号产生确定信号。

78. 发明申请

US20120104459A1 BI-DIRECTIONAL SCR ESD DEVICE 审中-公开
标题翻译：双向可控硅ESD器件
公开(公告)号：US20120104459A1
公开(公告)日：2012-05-03
申请号：US13345695
申请日：2012-01-07
申请人： Chih-Feng Huang
发明人： Chih-Feng Huang
IPC分类号： H01L29/73
CPC分类号： H01L27/0262 , H01L29/87
摘要： The present invention discloses a bi-directional SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a second well and a third well both located in the first well and both having a second conductivity type, the second well and the third well being separated from each other; a first high density doped region of the first conductivity type and a second high density doped region of the second conductivity type located in the second well; and a third high density doped region of the first conductivity type and a fourth high density doped region of the second conductivity type located in the third well.
摘要翻译：本发明公开了一种双向SCR ESD器件，包括：衬底; 位于衬底中的第一阱，其浮置并具有第一导电类型; 第二井和第三井都位于第一井中并且都具有第二导电类型，第二井和第三井彼此分离; 位于第二阱中的第一导电类型的第一高密度掺杂区和第二导电类型的第二高密度掺杂区; 以及位于第三阱中的第一导电类型的第三高密度掺杂区域和第二导电类型的第四高密度掺杂区域。

79. 发明授权

US07928509B2 Integrated JFET and schottky diode 有权
标题翻译：集成JFET和肖特基二极管
公开(公告)号：US07928509B2
公开(公告)日：2011-04-19
申请号：US12470391
申请日：2009-05-21
申请人： Chih-Feng Huang
发明人： Chih-Feng Huang
IPC分类号： H01L27/12
CPC分类号： H01L29/8083 , H01L27/0727 , H01L29/872
摘要： The present invention discloses an integrated junction field effect transistor (JFET) and Schottky diode, comprising a depletion mode JFET which includes a source, a drain and a gate, wherein the drain is not provided with an ohmic contact such that it forms a Schottky diode.
摘要翻译：本发明公开了一种集成结型场效应晶体管（JFET）和肖特基二极管，其包括耗尽型JFET，其包括源极，漏极和栅极，其中漏极没有提供欧姆接触，使得其形成肖特基二极管。

80. 发明授权

US07759769B2 Semiconductor structure of a high side driver 有权
标题翻译：高边驱动器的半导体结构
公开(公告)号：US07759769B2
公开(公告)日：2010-07-20
申请号：US11489558
申请日：2006-07-20
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L29/06
CPC分类号： H01L23/62 , H01L21/765 , H01L24/48 , H01L27/0805 , H01L29/0847 , H01L29/7835 , H01L2224/48091 , H01L2924/00014 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate and a deep well. The deep well is formed in the substrate and has a first concave structure. The ion-doped junction includes a semiconductor region connected to the first concave structure of the deep well and having substantially the same ion-doping concentration as the substrate.
摘要翻译：高侧驱动器的半导体结构包括离子掺杂结。离子掺杂结包括衬底和深阱。深孔形成在基板中并具有第一凹形结构。离子掺杂结包括连接到深阱的第一凹陷结构并且具有与衬底基本上相同的离子掺杂浓度的半导体区域。

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