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71. 发明授权

US06878920B2 Optical receiver circuit, method, and system 有权
标题翻译：光接收机电路，方法和系统
公开(公告)号：US06878920B2
公开(公告)日：2005-04-12
申请号：US10186311
申请日：2002-06-28
申请人： Bryan K. Casper , James E. Jaussi , Tanay Karnik
发明人： Bryan K. Casper , James E. Jaussi , Tanay Karnik
IPC分类号： H01J40/14 , H01L31/00
CPC分类号： H03F3/08
摘要： An optical receiver includes a photodiode, a variable current source, and a current mode comparator to detect a difference between current from the photodiode and current from the variable current source.
摘要翻译：光接收器包括光电二极管，可变电流源和电流模式比较器，用于检测来自光电二极管的电流与来自可变电流源的电流之间的差异。

72. 发明授权

US06617918B2 Multi-level receiver circuit with digital output using a variable offset comparator 有权
标题翻译：具有数字输出的多电平接收器电路，使用可变偏移比较器
公开(公告)号：US06617918B2
公开(公告)日：2003-09-09
申请号：US09968349
申请日：2001-09-28
申请人： Bryan K. Casper
发明人： Bryan K. Casper
IPC分类号： H03F102
CPC分类号： H03F3/45183 , H03F3/45672 , H03F2203/45371
摘要： A number of comparators are provided where each has a differential input coupled to receive a transmission line analog signal level. Each comparator has substantially variable offset that is controllable to represent a respective variable reference level, without requiring a separate input to receive a voltage reference level. An output of each comparator is to provide a value that represents a comparison between the transmission line analog signal level and the respective reference level.
摘要翻译：提供了多个比较器，其中每个具有耦合以接收传输线模拟信号电平的差分输入。每个比较器具有可变的偏移，其可控制以表示相应的可变参考电平，而不需要单独的输入来接收电压参考电平。每个比较器的输出是提供表示传输线模拟信号电平和相应参考电平之间的比较的值。

73. 发明授权

US06614301B2 Differential amplifier offset adjustment 有权
标题翻译：差分放大器偏移调整
公开(公告)号：US06614301B2
公开(公告)日：2003-09-02
申请号：US10062625
申请日：2002-01-31
申请人： Bryan K. Casper , James E. Jaussi
发明人： Bryan K. Casper , James E. Jaussi
IPC分类号： H03F345
CPC分类号： H03F3/45654 , H03F2203/45071 , H03F2203/45296 , H03F2203/45342 , H03K2217/0018
摘要： A differential amplifier includes a source coupled differential pair of transistors. A feedback loop detects the presence of an input referred offset in the differential amplifier and modifies a body bias voltage on at least one of the transistors in the differential pair. A comparator detects a differential output voltage when the differential input voltage is set to zero. In some embodiments, a charge pump in the feedback loop injects charge on the body of the transistor to modify the bias voltage. In other embodiments, a digital-to-analog converter receives a digital control word and produces a bias voltage on the body of the transistor.
摘要翻译：差分放大器包括源极耦合的差分对晶体管。反馈回路检测差动放大器中输入参考偏移的存在，并修改差分对中的至少一个晶体管上的体偏置电压。当差分输入电压设置为零时，比较器检测差分输出电压。在一些实施例中，反馈回路中的电荷泵将电荷注入到晶体管的主体上以修改偏置电压。在其他实施例中，数模转换器接收数字控制字，并在晶体管的主体上产生偏置电压。

74. 发明授权

US09362684B2 Rate scalable connector for high bandwidth consumer applications 有权
标题翻译：用于高带宽消费应用的速率可伸缩连接器
公开(公告)号：US09362684B2
公开(公告)日：2016-06-07
申请号：US13997096
申请日：2011-12-14
申请人： James E. Jaussi , Stephen R. Mooney , Howard L. Heck , Bruce E. Pederson , Bryan K. Casper
发明人： James E. Jaussi , Stephen R. Mooney , Howard L. Heck , Bruce E. Pederson , Bryan K. Casper
IPC分类号： H01R13/66 , H01R12/72 , H01R24/62
CPC分类号： H01R24/64 , H01R12/721 , H01R13/66 , H01R13/6658 , H01R24/28 , H01R24/62 , H01R2107/00
摘要： Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
摘要翻译：方法和系统可以包括具有集成缓冲器的输入/输出（IO）接口，壳体和设置在壳体内的基板。衬底可以包括第一侧，第二侧和连接边缘。集成缓冲器可以耦合到衬底的第一侧和第二侧中的至少一个。多个触点列可以耦合到衬底的第一侧。每排触点可以基本上平行于连接边缘堆叠。衬底可以具有耦合到其上的功率输出，并且集成缓冲器可以包括具有耦合到功率输出的电源输出的电压调节器。

75. 发明申请

US20140237142A1 BANDWIDTH CONFIGURABLE IO CONNECTOR 有权
标题翻译：带宽配置IO连接器
公开(公告)号：US20140237142A1
公开(公告)日：2014-08-21
申请号：US13995590
申请日：2011-09-30
申请人： James E. Jaussi , Stephen R. Mooney , Bryan K. Casper , Howard L. Heck
发明人： James E. Jaussi , Stephen R. Mooney , Bryan K. Casper , Howard L. Heck
IPC分类号： H04L12/24 , G06F13/38
CPC分类号： H04L41/0896 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device-side data lanes based on the bandwidth configuration command.
摘要翻译：互连设备的系统和方法可以包括具有一个或多个设备侧数据通道的输入/输出（IO）接口和用于接收带宽配置命令的收发机逻辑。收发器逻辑还可以基于带宽配置命令来配置一个或多个设备侧数据通道的发送带宽。此外，收发器逻辑可以基于带宽配置命令来配置一个或多个设备侧数据通道的接收带宽。

76. 发明授权

US08375242B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08375242B2
公开(公告)日：2013-02-12
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H04L27/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

77. 发明申请

US20110289341A1 CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS 有权
标题翻译：时钟和数据恢复（CDR）方法和装置
公开(公告)号：US20110289341A1
公开(公告)日：2011-11-24
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

78. 发明申请

US20110078340A1 VIRTUAL ROW BUFFERS FOR USE WITH RANDOM ACCESS MEMORY 有权
标题翻译：使用随机存取存储器的虚拟缓存
公开(公告)号：US20110078340A1
公开(公告)日：2011-03-31
申请号：US12567638
申请日：2009-09-25
申请人： CHANGKYU KIM , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
发明人： CHANGKYU KIM , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
IPC分类号： G06F12/00 , G06F3/00 , G06F13/00
CPC分类号： G11C11/4082 , G06F1/3275 , G11C11/4085 , Y02D10/13 , Y02D10/14
摘要： Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.
摘要翻译：降低存储芯片能量消耗的方法，装置和系统，同时在执行任何工作负载的同时增加其效果带宽。方法，设备和系统可以允许存储器芯片利用多个虚拟行缓冲器来响应包含在存储器阵列块中的数据的请求。方法，装置和系统可以通过改变存储器阵列块和行缓冲器之间的数据传输大小来进一步消除或减少与将不需要的数据从存储器阵列块传送到行缓冲器相关联的成本。

79. 发明授权

US07683729B2 Injection locked LC VCO clock deskewing 有权
标题翻译：注入锁定LC VCO时钟去歪斜
公开(公告)号：US07683729B2
公开(公告)日：2010-03-23
申请号：US11731776
申请日：2007-03-30
申请人： Mozhgan Mansuri , Sudip Shekhar , Bryan K. Casper , Frank P. O'Mahony
发明人： Mozhgan Mansuri , Sudip Shekhar , Bryan K. Casper , Frank P. O'Mahony
IPC分类号： H03K3/282
CPC分类号： H03L7/24 , H04L7/0008 , H04L7/0037 , H04L7/0276
摘要： In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.
摘要翻译：通常，在一个方面，本公开描述了一种包括感应电容性压控振荡器（LC VCO）以产生输出时钟的装置。电压/电流转换器用于接收转发的时钟并将转发的时钟注入LC VCO。输出时钟是转发时钟的偏斜版本。

80. 发明申请

US20090327788A1 CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS 有权
标题翻译：时钟和数据恢复（CDR）方法和装置
公开(公告)号：US20090327788A1
公开(公告)日：2009-12-31
申请号：US12165428
申请日：2008-06-30
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

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