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71. 发明授权

US06949433B1 Method of formation of semiconductor resistant to hot carrier injection stress 失效
标题翻译：形成半导体耐热载流子注入应力的方法
公开(公告)号：US06949433B1
公开(公告)日：2005-09-27
申请号：US10359872
申请日：2003-02-07
申请人： Shiraiwa Hidehiko , Arvind Halliyal , Jaeyong Park
发明人： Shiraiwa Hidehiko , Arvind Halliyal , Jaeyong Park
IPC分类号： H01L21/28 , H01L21/8247
CPC分类号： H01L21/28282 , Y10S438/954
摘要： The present invention, in one embodiment, relates to a process for fabricating a semiconductor device that is resistant to hot carrier induced stress. The method includes the steps of forming an oxide layer on a semiconductor substrate, the oxide layer and the semiconductor substrate forming a substrate-oxide interface, in which the interface includes at least one of silicon-hydrogen bonds or dangling silicon bonds; and exposing the interface to ultraviolet radiation and an atmosphere comprising at least one gas having at least atom capable of forming a silicon-atom bond under conditions sufficient to convert at least a portion of the at least one of silicon-hydrogen bonds or dangling silicon bonds to silicon-atom bonds.
摘要翻译：在一个实施例中，本发明涉及一种制造耐热载流子诱发应力的半导体器件的方法。该方法包括以下步骤：在半导体衬底上形成氧化物层，形成衬底 - 氧化物界面的氧化物层和半导体衬底，其中界面包括硅氢键或悬挂硅键中的至少一个; 以及将所述界面暴露于紫外线和包含至少一种具有至少能够形成硅原子键的原子的气体的气氛，所述条件足以转化至少一部分所述硅 - 氢键或悬挂硅键的至少一部分到硅原子键。

72. 发明授权

US06828162B1 System and method for active control of BPSG deposition 有权
标题翻译：用于主动控制BPSG沉积的系统和方法
公开(公告)号：US06828162B1
公开(公告)日：2004-12-07
申请号：US09894434
申请日：2001-06-28
申请人： Arvind Halliyal , Bhanwar Singh , Michael K. Templeton , Ramkumar Subramanian
发明人： Arvind Halliyal , Bhanwar Singh , Michael K. Templeton , Ramkumar Subramanian
IPC分类号： H01L2100
CPC分类号： H01L21/67253 , G01N21/4738 , H01L21/02129 , H01L21/31625
摘要： A system for monitoring and controlling a boron phosphorous doped silicon oxide (BPSG) deposition and reflow process is provided. The system includes one or more light sources, each light source directing light to one or more portions of a wafer upon which BPSG is deposited. Light reflected from the BPSG is collected by a measuring system, which processes the collected light. Light passing through the BPSG may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the conformality of the BPSG deposition of the respective portions of the wafer. The measuring system provides BPSG deposition related data to a processor that determines the BPSG deposition of the respective portions of the wafer. The system also includes a plurality of reflow controlling devices, each such device corresponding to a respective portion of the wafer and providing for the heating and/or cooling thereof. The processor selectively controls the reflow controlling devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译：提供了一种用于监测和控制硼磷掺杂氧化硅（BPSG）沉积和回流工艺的系统。该系统包括一个或多个光源，每个光源将光引导到沉积BPSG的晶片的一个或多个部分。从BPSG反射的光被测量系统收集，该系统处理收集的光。通过BPSG的光可以类似地由处理所收集的光的测量系统收集。所收集的光表示晶片的各个部分的BPSG沉积的一致性。测量系统将BPSG沉积相关数据提供给确定晶片各部分的BPSG沉积的处理器。该系统还包括多个回流控制装置，每个这样的装置对应于晶片的相应部分并提供加热和/或冷却。处理器选择性地控制回流控制装置，以便调节晶片各部分的温度。

73. 发明授权

US06774989B1 Interlayer dielectric void detection 失效
标题翻译：层间电介质空隙检测
公开(公告)号：US06774989B1
公开(公告)日：2004-08-10
申请号：US10050453
申请日：2002-01-16
申请人： Bharath Rangarajan , Michael K. Templeton , Arvind Halliyal , Bhanwar Singh
发明人： Bharath Rangarajan , Michael K. Templeton , Arvind Halliyal , Bhanwar Singh
IPC分类号： G01N2100
CPC分类号： G01N21/956 , G01N21/47
摘要： A system for detecting voids in an ILD layer is provided. The system includes one or more light sources, each light source directing light to respective portions of the ILD layer. Light reflected from the respective portions is collected by a measuring system that processes the collected light. The collected light is indicative of the presence of voids in the respective portions of the ILD layer. The measuring system provides ILD layer void related data to a processor that determines whether voids exist in the respective portions of the ILD layer. The processor selectively marks the ILD layer portions to facilitate further processing and/or destruction of the IC with the ILD layer voids.
摘要翻译：提供一种用于检测ILD层中的空隙的系统。该系统包括一个或多个光源，每个光源将光引导到ILD层的相应部分。通过处理收集的光的测量系统收集从各个部分反射的光。收集的光指示在ILD层的各个部分中存在空隙。测量系统向处理器提供ILD层空隙相关数据，该处理器确定在ILD层的相应部分中是否存在空隙。处理器选择性地标记ILD层部分以促进具有ILD层空隙的IC的进一步处理和/或破坏。

74. 发明授权

US06770523B1 Method for semiconductor wafer planarization by CMP stop layer formation 失效
标题翻译：通过CMP停止层形成的半导体晶片平面化方法
公开(公告)号：US06770523B1
公开(公告)日：2004-08-03
申请号：US10190397
申请日：2002-07-02
申请人： Kashmir S. Sahota , Jeffrey P. Erhardt , Arvind Halliyal , Minh Van Ngo , Krishnashree Achuthan
发明人： Kashmir S. Sahota , Jeffrey P. Erhardt , Arvind Halliyal , Minh Van Ngo , Krishnashree Achuthan
IPC分类号： H01L218238
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.
摘要翻译：提供了具有半导体晶片的集成电路的制造方法。化学机械抛光停止层沉积在半导体晶片上，并且在化学机械抛光停止层上处理第一光致抗蚀剂层。化学机械抛光停止层和半导体晶片被图案化以形成浅沟槽，浅沟槽隔离材料沉积在化学机械抛光停止层和浅沟槽中。在浅沟槽隔离材料上处理第二光致抗蚀剂层，留下未覆盖的浅沟槽。然后将未覆盖的浅沟槽处理成为化学机械抛光停止区域。然后将浅沟槽隔离材料进行化学机械抛光以与化学 - 机械停止层和化学 - 机械抛光停止处理区共面。

75. 发明授权

US06764966B1 Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric 有权
标题翻译：具有高K电介质的半导体器件具有渐变介电常数的间隔物
公开(公告)号：US06764966B1
公开(公告)日：2004-07-20
申请号：US10085278
申请日：2002-02-27
申请人： William George En , Arvind Halliyal , Ming-Ren Lin , Minh Van Ngo , Chih-Yuh Yang
发明人： William George En , Arvind Halliyal , Ming-Ren Lin , Minh Van Ngo , Chih-Yuh Yang
IPC分类号： H01L2128
CPC分类号： H01L29/6656 , H01L29/66833 , H01L29/78
摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.
摘要翻译：公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。半导体器件包括插入在栅电极和半导体衬底之间的电介质层。此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

76. 发明授权

US06750066B1 Precision high-K intergate dielectric layer 有权
标题翻译：精密高K隔间介电层
公开(公告)号：US06750066B1
公开(公告)日：2004-06-15
申请号：US10117818
申请日：2002-04-08
申请人： Fred TK Cheung , Arvind Halliyal
发明人： Fred TK Cheung , Arvind Halliyal
IPC分类号： H01I2120
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L21/3141 , H01L29/511
摘要： A semiconductor device which includes a precision high-K dielectric and formed on a semiconductor substrate and a method of forming the same. The semiconductor device includes at least one dielectric layer having a dielectric constant greater than SiO2. The at least one dielectric layer is deposited by atomic layer deposition (ALD). The ALD deposited layer has precise uniformity, thickness and abrupt atomic interfaces.
摘要翻译：一种包括精密高K电介质并形成在半导体衬底上的半导体器件及其形成方法。半导体器件包括介电常数大于SiO 2的至少一个电介质层。通过原子层沉积（ALD）沉积至少一个介电层。 ALD沉积层具有精确的均匀性，厚度和突然的原子界面。

77. 发明授权

US06731006B1 Doped copper interconnects using laser thermal annealing 失效
标题翻译：使用激光热退火的掺杂铜互连
公开(公告)号：US06731006B1
公开(公告)日：2004-05-04
申请号：US10323941
申请日：2002-12-20
申请人： Arvind Halliyal , Minh Van Ngo
发明人： Arvind Halliyal , Minh Van Ngo
IPC分类号： H01L2348
CPC分类号： H01L21/76802 , H01L21/76804 , H01L21/76807 , H01L21/76877 , H01L21/76886 , H01L23/5226 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of making the same includes a first metallization level, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer and the first etch stop layer. The first etch stop layer is disposed over the first metallization level. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. Dopants are introduced into the metal and are activated by laser thermal annealing. A concentration of the dopants within the metal in a lower portion of the second metal feature proximate the first metal feature is greater than a concentration of dopants in a central portion of the second metal feature, and a concentration of the dopants within the metal in an upper portion of the second metal feature is greater than a concentration of dopants in the central portion of the second metal feature.
摘要翻译：半导体器件及其制造方法包括第一金属化层，第一蚀刻停止层，电介质层和延伸穿过介电层和第一蚀刻停止层的开口。第一蚀刻停止层设置在第一金属化层上。开口内的金属形成第二金属特征，金属可以包括铜或铜合金。将掺杂剂引入金属中并通过激光热退火来激活。在第二金属特征附近的第二金属特征的下部中的金属内的掺杂剂的浓度大于第二金属特征的中心部分中的掺杂剂的浓度，并且金属中掺杂剂的浓度在第二金属特征的上部大于第二金属特征的中心部分中的掺杂剂的浓度。

78. 发明授权

US06727995B1 Gate oxide thickness measurement and control using scatterometry 有权
标题翻译：栅极氧化层厚度测量与控制采用散射法
公开(公告)号：US06727995B1
公开(公告)日：2004-04-27
申请号：US09903884
申请日：2001-07-12
申请人： Arvind Halliyal , Bhanwar Singh , Ramkumar Subramanian
发明人： Arvind Halliyal , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01B1106
CPC分类号： H01L21/28194 , G01B11/0625 , H01L21/67253 , H01L29/517 , H01L29/518
摘要： A system for regulating gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more gate oxide layers being deposited and/or formed on a wafer. Light reflected from the gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective gate oxide layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective gate oxide layers on the wafer. The system also includes a plurality of gate oxide layer formers where each gate oxide former corresponds to a respective portion of the wafer and provides for gate oxide layer formation thereon. The processor selectively controls the gate oxide layer formers to regulate gate oxide layer formation on the respective gate oxide layer formations on the wafer.
摘要翻译：提供了一种用于调节栅氧化层形成的系统。该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个栅极氧化物层。从栅极氧化层反射的光被测量系统收集，该系统处理所收集的光。所收集的光表示晶片上各个栅极氧化物层的厚度和/或均匀性。测量系统向处理器提供厚度和/或均匀性相关数据，其确定晶片上各个栅极氧化物层的厚度和/或均匀性。该系统还包括多个栅极氧化物层形成器，其中每个栅极氧化物形成体对应于晶片的相应部分并且在其上形成栅极氧化物层。处理器选择性地控制栅极氧化物层形成器以调节在晶片上的各个栅极氧化物层形成上的栅极氧化物层形成。

79. 发明授权

US06727176B2 Method of forming reliable Cu interconnects 失效
标题翻译：形成可靠的Cu互连的方法
公开(公告)号：US06727176B2
公开(公告)日：2004-04-27
申请号：US09986267
申请日：2001-11-08
申请人： Minh Van Ngo , Arvind Halliyal , Eric Paton
发明人： Minh Van Ngo , Arvind Halliyal , Eric Paton
IPC分类号： H01L2144
CPC分类号： H01L21/76882
摘要： Reliable Cu interconnects are formed by filling an opening in a dielectric layer with Cu and then laser thermal annealing in NH3 to reduce copper oxide and to reflow the deposited Cu, thereby eliminating voids and reducing contact resistance. Embodiments include laser thermal annealing employing an NH3 flow rate of about 200 to about 2,000 sccn.
摘要翻译：通过用Cu填充电介质层中的开口，然后在NH 3中激光热退火以形成可靠的Cu互连，以减少氧化铜和回流沉积的Cu，从而消除空隙并降低接触电阻。实施例包括使用约200至约2,000sccn的NH 3流速的激光热退火。

80. 发明授权

US06589804B1 Oxide/nitride or oxide/nitride/oxide thickness measurement using scatterometry 失效
标题翻译：使用散射测量的氧化物/氮化物或氧化物/氮化物/氧化物厚度测量
公开(公告)号：US06589804B1
公开(公告)日：2003-07-08
申请号：US09904089
申请日：2001-07-12
申请人： Arvind Halliyal , Bhanwar Singh , Ramkumar Subramanian
发明人： Arvind Halliyal , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L2100
CPC分类号： G01B11/0625
摘要： A system for regulating ON and/or ONO dielectric formation is provided. The system includes one or more light sources, each light source directing light to one or more oxide and/or nitride layers being deposited and/or formed on a wafer. Light reflected from the oxide and/or nitride layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The system also includes a plurality of oxide/nitride formers; each oxide/nitride former corresponding to a respective portion of the wafer and providing for ON and/or ONO formation thereon. The processor selectively controls the oxide/nitride formers to regulate oxide and/or nitride layer formation on the respective ON and/or ONO formations on the wafer.
摘要翻译：提供了一种用于调节ON和/或ONO电介质形成的系统。该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个氧化物和/或氮化物层。从氧化物和/或氮化物层反射的光被测量系统收集，该系统处理收集的光。所收集的光指示晶片上各个氧化物和/或氮化物层的厚度和/或均匀性。测量系统向处理器提供厚度和/或均匀性相关数据，其确定晶片上相应氧化物和/或氮化物层的厚度和/或均匀性。该系统还包括多个氧化物/氮化物成形器; 每个氧化物/氮化物成形器对应于晶片的相应部分并且在其上提供ON和/或ONO形成。处理器选择性地控制氧化物/氮化物成形器以调节晶片上相应的ON和/或ONO形成上的氧化物和/或氮化物层的形成。

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