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71. 发明授权

US07547954B2 Electronic systems using optical waveguide interconnects formed through a semiconductor wafer 有权
标题翻译：使用通过半导体晶片形成的光波导互连的电子系统
公开(公告)号：US07547954B2
公开(公告)日：2009-06-16
申请号：US11653501
申请日：2007-01-16
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L31/0232
CPC分类号： G02B6/032 , G02B6/12002 , G02B6/136 , G02B6/42 , G02B6/43
摘要： An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
摘要翻译：具有形成在高纵横比孔中的多个光波导的集成电路。高纵横比孔延伸穿过半导体晶片。光波导包括高反射材料，其被沉积以便可以填充空气的高纵横比孔的内表面或具有大于1的折射率的材料。这些金属限制波导被使用以在半导体晶片上的功能电路和晶片的背面或晶片之下的功能电路之间传输信号。

72. 发明授权

US07544989B2 High density stepped, non-planar flash memory 有权
公开(公告)号：US07544989B2
公开(公告)日：2009-06-09
申请号：US11472617
申请日：2006-06-22
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L29/94
CPC分类号： H01L27/11553 , G11C16/0483 , H01L27/11521 , H01L27/11551
摘要： A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series connection of their source/drain regions.

73. 发明申请

US20090137067A1 METHOD FOR FORMING AN INDUCTOR 审中-公开
标题翻译：形成电感器的方法
公开(公告)号：US20090137067A1
公开(公告)日：2009-05-28
申请号：US12362621
申请日：2009-01-30
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L21/02
CPC分类号： H01L23/5227 , H01F17/0013 , H01L2924/0002 , H01L2924/3011 , Y10T29/4902 , Y10T29/4906 , Y10T29/49064 , Y10T29/49069 , Y10T29/49155 , H01L2924/00
摘要： A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors.
摘要翻译：在半导体衬底之上制造的螺旋电感器在仅占用小的表面积的同时提供大的电感。在电感上方和下方包括一层磁性材料会增加电感的电感。磁性材料也作为将螺旋电感器中产生的电子噪声限制在螺旋电感器占据的区域的屏障。通过在堆叠的螺旋电感器之间包括一层磁性材料，增加了一对叠层螺旋电感器中的电感。

74. 发明授权

US07489002B2 Memory having a vertical transistor 有权
标题翻译：存储器具有垂直晶体管
公开(公告)号：US07489002B2
公开(公告)日：2009-02-10
申请号：US11059723
申请日：2005-02-16
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/78642 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/1203 , H01L29/0653 , H01L29/66666 , H01L29/7827
摘要： Structures and fabrication methods for a memory are provided. The memory includes an array of memory cells, where each memory cell has a pillar extending outwardly from a substrate. The pillar includes a first contact layer and a second contact layer separated by an insulating layer. A transistor is formed along side of the pillar. A plurality of buried bit lines are formed of semiconductor material and disposed below the pillars in the array memory cells to interconnect the first contact layer of column adjacent pillars in the array of memory cells. In an embodiment, each word line of a plurality of word lines is disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars to address gates of the transistors that are adjacent to the trench.
摘要翻译：提供了存储器的结构和制造方法。存储器包括存储器单元的阵列，其中每个存储器单元具有从衬底向外延伸的柱。该柱包括由绝缘层分隔开的第一接触层和第二接触层。晶体管沿着支柱的一侧形成。多个掩埋位线由半导体材料形成并且设置在阵列存储单元中的柱下方以互连存储器单元阵列中的相邻柱的第一接触层。在一个实施例中，多个字线的每个字线与柱的行之间的沟槽中的多个掩埋位线正交地设置为与沟槽相邻的晶体管的栅极。

75. 发明申请

US20090032910A1 DIELECTRIC STACK CONTAINING LANTHANUM AND HAFNIUM 有权
标题翻译：含有镧和铪的电介质堆
公开(公告)号：US20090032910A1
公开(公告)日：2009-02-05
申请号：US12177668
申请日：2008-07-22
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L23/58 , H01L21/31 , H01L21/20 , H01L21/336
CPC分类号： H01L21/02181 , C23C16/40 , C23C16/45531 , C23C16/45553 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L21/3141 , H01L21/31645 , H01L2924/0002 , H01L2924/00
摘要： Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
摘要翻译：包含镧和铪的电介质层的介电层和制造这种电介质层的方法提供了用于各种电子器件的各种结构的绝缘层。

76. 发明授权

US07465983B2 Low tunnel barrier insulators 有权
标题翻译：低隧道隔离绝缘子
公开(公告)号：US07465983B2
公开(公告)日：2008-12-16
申请号：US11708438
申请日：2007-02-20
申请人： Jerome M. Eldridge , Kie Y. Ahn , Leonard Forbes
发明人： Jerome M. Eldridge , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L29/76
CPC分类号： H01L27/11556 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/66825 , H01L29/7885
摘要： Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
摘要翻译：提供了具有不对称低隧道势垒隔离绝缘子的可编程阵列型逻辑和/或存储器件的结构和方法。可编程阵列型逻辑和/或存储器件包括具有第一源极/漏极区域和由衬底中的沟道区域分开的第二源极/漏极区域的非易失性存储器。与沟道区相对的浮栅，并由栅极氧化物分离。控制门反对浮动门。控制栅极通过由原子层沉积物形成的不对称的低隧道势垒隔间绝缘体与浮动栅极分离。非对称低隧道势垒隔间绝缘体包括选自Al2O3，Ta2O5，TiO2，ZrO2，Nb2O5，SrBi2Ta2O3，SrTiO3，PbTiO3和PbZrO3的金属氧化物绝缘体。

77. 发明授权

US07465982B2 Capacitor structures 有权
标题翻译：电容结构
公开(公告)号：US07465982B2
公开(公告)日：2008-12-16
申请号：US10931544
申请日：2004-08-31
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L27/108
CPC分类号： H01L21/022 , H01L21/02175 , H01L21/02181 , H01L21/02192 , H01L21/02244 , H01L21/28185 , H01L21/28194 , H01L21/28229 , H01L21/31683 , H01L27/1085 , H01L27/10873 , H01L28/40 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-containing layer is first formed and that treated to form a dielectric layer. Dielectric layers formed by methods of the present invention have a dielectric constant greater than that of silicon dioxide, and can have an equivalent oxide thickness of less than 2 nanometers. Such dielectric layers are useful in the forming of a variety of semiconductor devices such as transistors, capacitors and the like where such devices and integrated circuits formed from such devices are encompassed by embodiments in accordance with the present invention.
摘要翻译：根据本发明的实施例提供了作为电介质层有效的替代材料和形成这种材料的方法。这样的实施例包括在含硅基底上形成含金属的电介质层，其中首先形成含金属的层并且被处理以形成电介质层。通过本发明的方法形成的介电层的介电常数大于二氧化硅的介电常数，并且可具有小于2纳米的等效氧化物厚度。这样的电介质层可用于形成诸如晶体管，电容器等的各种半导体器件，其中由这些器件形成的器件和集成电路包括在根据本发明的实施例中。

78. 发明申请

US20080283940A1 LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS 有权
标题翻译：低温高品质超薄CoTiO3门电介质
公开(公告)号：US20080283940A1
公开(公告)日：2008-11-20
申请号：US12176949
申请日：2008-07-21
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L21/02252 , C23C14/16 , C23C14/5826 , C23C14/5853 , H01L21/02197 , H01L21/02244 , H01L21/28194 , H01L21/28211 , H01L21/31683 , H01L21/823462 , H01L27/10873 , H01L29/517
摘要： A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which inhibits unwanted species migration and unwanted reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
摘要翻译：提供栅极氧化物和制造栅极氧化物的方法，其产生比常规SiO 2栅极氧化物更可靠和更薄的等效氧化物厚度。由钴 - 钛合金形成的栅氧化物是热力学稳定的，使得形成的栅极氧化物在任何后续高温处理阶段中与硅衬底或其它结构的反应将最小化。所示的方法在比现有技术更低的温度下进行，其抑制不需要的物质迁移和与硅衬底或其它结构的不期望的反应。使用热蒸发技术沉积要被氧化的层，保留下面的基底表面的光滑度，从而在所得的栅极氧化物中提供改进的和更一致的电性能。

79. 发明申请

US20080265243A1 Magnetic floating gate flash memory structures 审中-公开
标题翻译：磁浮栅闪存结构
公开(公告)号：US20080265243A1
公开(公告)日：2008-10-30
申请号：US11796750
申请日：2007-04-30
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L29/06 , H01L21/3205
CPC分类号： H01L43/08 , B82Y10/00 , C23C16/18 , C23C16/45525 , G11C11/16 , H01L27/228 , H01L29/40114 , H01L43/12
摘要： Methods of forming ferromagnetic floating gate structures are described. The methods include atomic layer deposition of multiple precursor films, followed by alloying the metals in the precursor films, to form a ferromagnetic floating gate. Devices that include ferromagnetic floating gates formed with these methods are also described.
摘要翻译：描述形成铁磁浮栅结构的方法。这些方法包括多个前体膜的原子层沉积，然后将前体膜中的金属合金化，以形成铁磁浮栅。还描述了包括用这些方法形成的铁磁浮动栅极的装置。

80. 发明申请

US20080246578A1 OPEN PATTERN INDUCTOR 有权
标题翻译：开放图案电感器
公开(公告)号：US20080246578A1
公开(公告)日：2008-10-09
申请号：US12120144
申请日：2008-05-13
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01F5/00 , H01F7/06
CPC分类号： H01L28/10 , H01F17/0013 , H01F27/365 , H01F41/043 , H01F41/046 , H01L27/08 , H01P9/02 , H01P11/007 , Y10T29/4902 , Y10T29/4906 , Y10T29/49062 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075
摘要： Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.
摘要翻译：各种实施例包括在半导体衬底上方制造的堆叠开式图案电感器。堆叠的开放式图案电感器包括嵌入在磁性氧化物或绝缘体中的多个平行开放的导电图案和磁性材料。将堆叠的开路图案电感器嵌入磁性氧化物或绝缘体和磁性材料中增加了电感器的电感，并允许磁通量被限制在电感器的区域。一层磁性材料可以位于电感器上方和电感器下方，以将堆叠的开放式图案电感器中产生的电子噪声限制在电感器占据的面积上。可以使用传统的集成电路制造工艺来制造堆叠的开放式图案电感器，并且电感器可以与计算机系统结合使用。

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