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71. 发明授权

US4618262A Laser interferometer system and method for monitoring and controlling IC processing 失效
标题翻译：激光干涉仪系统及IC处理监控与控制方法
公开(公告)号：US4618262A
公开(公告)日：1986-10-21
申请号：US600189
申请日：1984-04-13
申请人： Dan Maydan , Sasson Somekh , Edward M. Kaczorowski
发明人： Dan Maydan , Sasson Somekh , Edward M. Kaczorowski
IPC分类号： H01L21/302 , G01B11/06 , H01L21/3065 , H01L21/31 , H01L21/66 , G01B11/02 , G01B9/02
CPC分类号： G01B11/0675
摘要： A laser interferometer system and associated method for etching endpoint detection, and for monitoring etching or growth to a selected depth. The process implemented by the system involves scanning the laser beam across scribe lines on a wafer which is undergoing fabrication (growth or etching) and monitoring the resulting interference pattern. Alternatively, the process implemented by this system involves moving the laser beam across the scribe line to detect the position of the scribe line; locking the laser beam on the scribe line; and monitoring the resulting interference pattern.
摘要翻译：激光干涉仪系统和相关方法，用于蚀刻端点检测，以及用于监测蚀刻或生长至选定深度。该系统实现的过程包括扫描正在进行制造（生长或蚀刻）的晶片上的划线上的激光束并监测所得到的干涉图案。或者，由该系统实现的过程包括将激光束移动穿过划线以检测划线的位置; 将激光束锁定在划线上; 并监测产生的干扰模式。

72. 发明授权

US4383885A Reactive sputter etching of polysilicon utilizing a chlorine etch gas 失效
标题翻译：使用氯气气体对多晶硅进行反应溅射蚀刻
公开(公告)号：US4383885A
公开(公告)日：1983-05-17
申请号：US300307
申请日：1981-09-08
申请人： Dan Maydan , David N. Wang
发明人： Dan Maydan , David N. Wang
IPC分类号： C04B41/53 , H01L21/3065 , H01L21/3213 , H01L21/308
CPC分类号： C04B41/5346 , H01L21/3065 , H01L21/32137
摘要： In a chlorine plasma, reactive sputter etching of monocrystalline silicon, undoped polycrystalline silicon or doped polycrystalline silicon is achieved. The etching processes are substantially free of any loading effects and are characterized by high resolution, excellent uniformity and high selectivity with respect to, for example, silicon dioxide. For silicon and undoped polysilicon, the edge profile of the etched material is anisotropic. For doped polysilicon, the edge profile can be controlled to occur anywhere in the range from completely isotropic to completely anisotropic.
摘要翻译：在氯等离子体中，实现了单晶硅，未掺杂多晶硅或掺杂多晶硅的反应溅射蚀刻。蚀刻工艺基本上没有任何负载效应，其特征在于相对于例如二氧化硅的高分辨率，优异的均匀性和高选择性。对于硅和未掺杂的多晶硅，蚀刻材料的边缘轮廓是各向异性的。对于掺杂多晶硅，可以将边缘轮廓控制在从完全各向同性到完全各向异性的范围内的任何地方。

73. 发明授权

US4185202A X-ray lithography 失效
标题翻译： X射线光刻
公开(公告)号：US4185202A
公开(公告)日：1980-01-22
申请号：US857380
申请日：1977-12-05
申请人： Robert E. Dean , Dan Maydan , Joseph M. Moran , Gary N. Taylor
发明人： Robert E. Dean , Dan Maydan , Joseph M. Moran , Gary N. Taylor
IPC分类号： H01L21/30 , G03F7/20 , G21K5/02 , A61K27/02 , A61N5/00 , C08J1/02 , G21G5/00
CPC分类号： G03F7/70866 , G03F7/2039 , G03F7/70933
摘要： X-ray lithographic systems as heretofore constructed include a low-attenuation chamber for propagating x-rays from a source toward a mask member that is positioned in close proximity to a resist-coated wafer. Both the mask and the wafer are included in the chamber which typically is either filled with helium or evacuated to a pressure less than about 10.sup.-2 Torr. In accordance with this invention, an x-ray lithographic system is constructed to enable establishment in the wafer-to-mask region of a controlled atmosphere that is separate and distinct from that maintained in the low-attenuation chamber. In this way, an improved lithographic system with advantageous throughput and other characteristics is realized.
摘要翻译：如前所述构造的X射线光刻系统包括用于将X射线从源极传递到靠近抗蚀剂涂覆晶片的掩模构件的低衰减室。掩模和晶片都包括在通常用氦填充或抽空到小于约10-2乇的压力的室中。根据本发明，x射线光刻系统被构造成使得能够建立与被保持在低衰减室中的受控气氛分开且不同的受控气氛的晶片到掩模区域。以这种方式，实现了具有有利吞吐量和其它特性的改进的光刻系统。

74. 发明授权

US07431585B2 Apparatus and method for heating substrates 失效
公开(公告)号：US07431585B2
公开(公告)日：2008-10-07
申请号：US10278615
申请日：2002-10-22
申请人： Jun Zhao , David Quach , Timothy Weidman , Rick J. Roberts , Farhad Moghadam , Dan Maydan
发明人： Jun Zhao , David Quach , Timothy Weidman , Rick J. Roberts , Farhad Moghadam , Dan Maydan
IPC分类号： F27D3/00
CPC分类号： H01L21/67109 , Y10S414/139
摘要： An apparatus for processing substrates is disclosed. In one embodiment, the apparatus includes a housing and a plurality of stacked cell structures in the housing. An actuator is adapted to move the plurality of stacked cell structures inside of the housing while substrates in the stacked cell structures are being heated.

75. 发明授权

US07087179B2 Optical integrated circuits (ICs) 有权
标题翻译：光集成电路（IC）
公开(公告)号：US07087179B2
公开(公告)日：2006-08-08
申请号：US09734950
申请日：2000-12-11
申请人： Cecilia Y. Mak , John M. White , Kam S. Law , Dan Maydan
发明人： Cecilia Y. Mak , John M. White , Kam S. Law , Dan Maydan
IPC分类号： B29D11/00
CPC分类号： G02B6/12004 , G02B6/13 , G02B6/132
摘要： In one aspect, the invention provides methods and apparatus for forming optical devices on large area substrates. The large area substrates are preferably made of quartz, silica or fused silica. The large area substrates enable larger optical devices to be formed on a single die. In another aspect, the invention provides methods and apparatus for forming integrated optical devices on large area substrates, such as quartz, silica or fused silica substrates. In another aspect, the invention provides methods and apparatus for forming optical devices using damascene techniques on large area substrates or silicon substrates. In another aspect, methods for forming optical devices by bonding an upper cladding layer on a lower cladding and a core is provided.
摘要翻译：一方面，本发明提供了用于在大面积基板上形成光学装置的方法和装置。大面积基板优选由石英，二氧化硅或熔融二氧化硅制成。大面积基板使得能够在单个管芯上形成更大的光学器件。另一方面，本发明提供了用于在大面积衬底（例如石英，二氧化硅或熔融二氧化硅衬底）上形成集成光学器件的方法和装置。在另一方面，本发明提供了使用大面积衬底或硅衬底上的镶嵌技术形成光学器件的方法和装置。在另一方面，提供了通过将下包层和芯上的上包层结合来形成光器件的方法。

76. 发明授权

US07072534B2 Optical ready substrates 失效
标题翻译：光学就绪基板
公开(公告)号：US07072534B2
公开(公告)日：2006-07-04
申请号：US10280505
申请日：2002-10-25
申请人： Claes Björkman , Lawrence C. West , Dan Maydan , Samuel Broydo
发明人： Claes Björkman , Lawrence C. West , Dan Maydan , Samuel Broydo
IPC分类号： G02B6/12
CPC分类号： G02B6/12004 , G02B6/12 , G02B6/30 , G02B6/4214 , G02B6/4245 , G02B6/4257 , G02B6/4274 , G02B6/4283 , G02B6/43
摘要： An article of manufacture comprising an optical ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.
摘要翻译：一种制品，包括由第一半导体层制成的光学就绪衬底，在第一半导体层的顶部上的绝缘层和在绝缘层的顶部上的第二半导体层，其中第二半导体层具有顶表面，并且是横向分为包括第一区域和第二区域的两个区域，第一区域的顶表面的质量足以允许在其中形成微电子电路，并且第二区域包括其中形成的光信号分配电路，光信号分配电路由互连的半导体光子元件组成，并被设计为向要在第二半导体层的第一区域中制造的微电子电路提供信号。

77. 发明授权

US06893907B2 Fabrication of silicon-on-insulator structure using plasma immersion ion implantation 失效
标题翻译：使用等离子体浸没离子注入制造绝缘体上硅结构
公开(公告)号：US06893907B2
公开(公告)日：2005-05-17
申请号：US10786410
申请日：2004-02-24
申请人： Dan Maydan , Randir P. S. Thakur , Kenneth S. Collins , Amir Al-Bayati , Hiroji Hanawa , Kartik Ramaswamy , Biagio Gallo , Andrew Nguyen
发明人： Dan Maydan , Randir P. S. Thakur , Kenneth S. Collins , Amir Al-Bayati , Hiroji Hanawa , Kartik Ramaswamy , Biagio Gallo , Andrew Nguyen
IPC分类号： H01J37/32 , H01L21/00
CPC分类号： H01J37/321 , H01J2237/0825 , Y10S438/977
摘要： A method of fabricating a silicon-on-insulator structure having a silicon surface layer in a semiconductor workpiece, is carried out by maintaining the workpiece at an elevated temperature and producing an oxygen-containing plasma in the chamber while applying a bias to the workpiece and setting the bias to a level corresponding to an implant depth in the workpiece below the silicon surface layer to which oxygen atoms are to be implanted, whereby to form an oxygen-implanted layer in the workpiece having an oxygen concentration distribution generally centered at the implant depth and having a finite oxygen concentration in the silicon surface layer. The oxygen concentration in the silicon surface layer is then reduced to permit epitaxial silicon deposition.
摘要翻译：在半导体工件中制造具有硅表面层的绝缘体上硅结构的方法通过将工件保持在升高的温度下并在室中产生含氧等离子体，同时向工件施加偏压，将所述偏压设置为与待注入氧原子的硅表面层下方的所述工件中的植入深度相对应的水平，由此在所述工件中形成氧注入层，所述氧注入层通常以注入深度为中心并且在硅表面层中具有有限的氧浓度。然后减小硅表面层中的氧浓度以允许外延硅沉积。

78. 发明申请

US20050072979A1 Optical-ready wafers 审中-公开
标题翻译：光学准备晶圆
公开(公告)号：US20050072979A1
公开(公告)日：2005-04-07
申请号：US10623665
申请日：2003-07-21
申请人： Lawrence West , Dan Maydan , Samuel Broydo , Claes Bjorkman
发明人： Lawrence West , Dan Maydan , Samuel Broydo , Claes Bjorkman
IPC分类号： G02B6/12 , G02B6/30 , G02B6/42 , G02B6/43 , H01L27/15
CPC分类号： G02B6/12 , G02B6/12004 , G02B6/30 , G02B6/4201 , G02B6/4214 , G02B6/4245 , G02B6/4257 , G02B6/4274 , G02B6/4283 , G02B6/43
摘要： An optical-ready substrate made at least in part of a first semiconductor material and having a front side and a backside, the front side having a top surface that is of sufficient quality to permit microelectronic circuitry to be fabricated thereon using semiconductor fabrication processing techniques. The optical-ready substrate includes an optical signal distribution circuit fabricated on the front side of the substrate in a first layer region beneath the top surface of the substrate. The optical signal distribution circuit is made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuitry to be fabricated thereon.
摘要翻译：至少部分由第一半导体材料制成且具有正面和背面的光学就绪衬底，其前侧具有足够质量的顶表面，以允许使用半导体制造处理技术在其上制造微电子电路。光学就绪衬底包括在衬底的顶表面下方的第一层区域中制造在衬底的前侧上的光信号分配电路。光信号分配电路由互连的半导体光子元件组成，并被设计成向要在其上制造的微电子电路提供信号。

79. 发明授权

US06503375B1 Electroplating apparatus using a perforated phosphorus doped consumable anode 失效
标题翻译：使用穿孔磷掺杂的消耗性阳极的电镀设备
公开(公告)号：US06503375B1
公开(公告)日：2003-01-07
申请号：US09503156
申请日：2000-02-11
申请人： Dan Maydan , Ashok K. Sinha
发明人： Dan Maydan , Ashok K. Sinha
IPC分类号： C25B900
CPC分类号： H01L21/76843 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/76873
摘要： The present invention generally provides an apparatus for forming a doped metal film on a conductive substrate. In one aspect of the invention, an apparatus is provided that includes a phosphorus doped anode used for depositing a phosphorus doped metal film, such as a seed layer, in an electrochemical deposition process. The phosphorus doped anode preferably includes an enclosure providing for flow of an electrolyte therethrough, a phosphorus doped metal disposed within the enclosure, and an electrode disposed through the enclosure and in electrical connection with the phosphorus doped metal. Another aspect of the invention provides an apparatus for electrochemical deposition of a phosphorus doped metal onto a substrate includes a substrate holder adapted to hold the substrate in a position where the substrate plating surface is exposed to an electrolyte in an electrolyte container, a cathode electrically contacting the substrate plating surface, an electrolyte container having an electrolyte inlet, an electrolyte outlet and an opening adapted to receive the substrate plating surface, and a phosphorus doped anode electrically connected to the electrolyte.
摘要翻译：本发明通常提供一种用于在导电衬底上形成掺杂金属膜的装置。在本发明的一个方面，提供一种装置，其包括用于在电化学沉积工艺中沉积磷掺杂金属膜例如种子层的磷掺杂阳极。磷掺杂阳极优选地包括提供电解质流过的外壳，设置在外壳内的磷掺杂金属，以及通过外壳设置并与磷掺杂金属电连接的电极。本发明的另一方面提供了一种用于将磷掺杂金属电化学沉积到衬底上的设备，包括：衬底保持器，其适于将衬底保持在电镀液容器中的电解质暴露于衬底镀层表面的位置，阴极电接触基板电镀表面，具有电解质入口的电解质容器，电解液出口和适于接收基板电镀表面的开口，以及电连接到电解质的磷掺杂阳极。

80. 再颁专利

USRE36623E Process for PECVD of silicon oxide using TEOS decomposition 失效
公开(公告)号：USRE36623E
公开(公告)日：2000-03-21
申请号：US752972
申请日：1996-12-02
申请人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , C23C16/509 , C23C16/54 , H01L21/314 , H01L21/316 , H05H1/24
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surface. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the sane reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

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