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1. 发明授权

US07220685B2 Method for depositing porous films 有权
标题翻译：沉积多孔膜的方法
公开(公告)号：US07220685B2
公开(公告)日：2007-05-22
申请号：US11483034
申请日：2006-07-07
申请人： Cecilia Y. Mak , Kam S. Law
发明人： Cecilia Y. Mak , Kam S. Law
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/3124 , H01L21/31625 , H01L21/31629 , H01L21/31695 , H01L2221/1047
摘要： A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon from the codeposit to form a porous structure. In a preferred embodiment, the codeposition is carried out by plasma enhanced chemical vapor deposition. After codeposition, the codeposit is exposed to a selective silicon removal reagent that can preferentially remove the silicon in the codeposit, leaving behind a porous structure. Repeated execution of the codeposition and the selective silicon removal steps build up thickness of the porous film. A porous film with highly uniform small pores and a desired porosity profile can be obtained with this method. This method is advantageous for forming a broad range of low-k dielectrics for semiconductor integrated circuit fabrication. The general method is also advantageous for forming other porous films for other applications.
摘要翻译：提供了一种用于沉积多孔二氧化硅和掺杂二氧化硅膜的方法。该方法使用循环方案，其中每个循环包括首先将二氧化硅与硅共沉积，然后从共沉积物中选择性除去硅以形成多孔结构。在优选的实施方案中，共沉积通过等离子体增强化学气相沉积进行。共沉积后，共沉积物暴露于选择性硅去除剂，其可优先除去共沉积物中的硅，留下多孔结构。重复执行共沉积和选择性硅去除步骤建立了多孔膜的厚度。使用该方法可以获得具有高度均匀的小孔和所需孔隙率分布的多孔膜。该方法有利于形成用于半导体集成电路制造的宽范围的低k电介质。一般方法对于形成用于其它应用的其它多孔膜也是有利的。

2. 发明授权

US07132374B2 Method for depositing porous films 有权
标题翻译：沉积多孔膜的方法
公开(公告)号：US07132374B2
公开(公告)日：2006-11-07
申请号：US10920602
申请日：2004-08-17
申请人： Cecilia Y. Mak , Kam S. Law
发明人： Cecilia Y. Mak , Kam S. Law
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/3124 , H01L21/31625 , H01L21/31629 , H01L21/31695 , H01L2221/1047
摘要： A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon to form a porous structure. In a preferred embodiment, the codeposition is carried out by plasma enhanced chemical vapor deposition. The reagent feed stream comprises a mixture of codeposition reagents and a selective silicon removal reagent. RF power modulation is used to control the codeposition and the selective silicon removal steps with the later proceeds whenever the RF power is turned off or reduced to a low level. A porous film with highly uniform small pores and a desired porosity profile can be obtained with this method. This method is advantageous for forming a broad range of low-k dielectrics for semiconductor integrated circuit fabrication. The method is also advantageous for forming other porous films for other applications.
摘要翻译：提供了一种用于沉积多孔二氧化硅和掺杂二氧化硅膜的方法。该方法使用循环方案，其中每个循环包括首先将二氧化硅与硅共沉积，然后选择性地除去硅以形成多孔结构。在优选的实施方案中，共沉积通过等离子体增强化学气相沉积进行。试剂进料流包含共沉积试剂和选择性硅去除试剂的混合物。 RF功率调制用于控制共沉积和选择性硅去除步骤，随着RF功率关闭或降低到低电平，随后进行。使用该方法可以获得具有高度均匀的小孔和所需孔隙率分布的多孔膜。该方法有利于形成用于半导体集成电路制造的宽范围的低k电介质。该方法对于形成用于其它应用的其它多孔膜也是有利的。

3. 发明授权

US07056830B2 Method for plasma etching a dielectric layer 失效
标题翻译：等离子体蚀刻电介质层的方法
公开(公告)号：US07056830B2
公开(公告)日：2006-06-06
申请号：US10655231
申请日：2003-09-03
申请人： Walter R. Merry , Cecilia Y. Mak , Kam S. Law
发明人： Walter R. Merry , Cecilia Y. Mak , Kam S. Law
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/30655 , H01L21/31116
摘要： A method of etching a dielectric layer formed on a substrate including a sequence of processing cycles, wherein each cycle comprises steps of depositing an inactive polymeric film, activating the film to etch the structure, and removing the film is disclosed. In one embodiment, the method uses a fluorocarbon gas to form the polymeric film and a substrate bias to activate such film.
摘要翻译：一种蚀刻在衬底上形成的包括一系列处理循环的电介质层的方法，其中每个循环包括沉积非活性聚合物膜，激活该膜以蚀刻该结构并除去该膜的步骤。在一个实施方案中，该方法使用碳氟化合物气体来形成聚合物膜和衬底偏压以激活这种膜。

4. 发明授权

US5596661A Monolithic optical waveguide filters based on Fourier expansion 失效
标题翻译：基于傅里叶扩展的单片光波导滤波器
公开(公告)号：US5596661A
公开(公告)日：1997-01-21
申请号：US365618
申请日：1994-12-28
申请人： Charles H. Henry , Edward J. Laskowski , Yuan P. Li , Cecilia Y. Mak , Henry H. Yaffe
发明人： Charles H. Henry , Edward J. Laskowski , Yuan P. Li , Cecilia Y. Mak , Henry H. Yaffe
IPC分类号： G02B6/12 , G02B6/28 , G02B6/34 , H01S3/10 , H04J14/02 , C02B6/28
CPC分类号： G02B6/2938 , G02B6/12007 , G02B6/29355 , H01S3/10023 , H04J14/0201 , G02B6/2861 , H01S2301/04 , H04J14/02 , H04J14/0208 , H04J14/0209
摘要： In accordance with the invention, a new type of monolithic optical waveguide filter comprises a chain of optical couplers of different effective lengths linked by differential delays of different lengths. The transfer of the chain of couplers and delays is the sum of contributions from all possible optical paths, each contribution forming a term in a Fourier series whose sum forms the optical output. A desired frequency response is obtained by optimizing the lengths of the couplers and the delay paths so that the Fourier series best approximates the desired response. The filter is advantageously optimized so that it is insensitive to uncontrolled fabrication errors and is short in length. The wavelength dependence of practical waveguide properties is advantageously incorporated in the optimization. Consequently, the filter is highly manufacturable by mass production. Such filters have been shown to meet the requirements for separating the 1.3 and 1.551 .mu.m telecommunications channels and for flattening the gain of Er amplifiers.
摘要翻译：根据本发明，新型单片光波导滤波器包括通过不同长度的差分延迟链接的不同有效长度的光耦合器链。耦合器链和延迟的传输是来自所有可能的光路的贡献的总和，每个贡献形成傅立叶级数中的项，其和形成光输出。通过优化耦合器的长度和延迟路径来获得期望的频率响应，使得傅立叶级数最佳地近似于期望的响应。滤波器有利地被优化，使得其对不受控制的制造误差不敏感并且长度短。实际波导特性的波长依赖性有利地结合在优化中。因此，过滤器通过批量生产高度可制造。已经显示出这种滤波器符合分离1.3和1.551 m通信信道的要求，并使Er放大器的增益变扁平。

5. 发明授权

US07087179B2 Optical integrated circuits (ICs) 有权
标题翻译：光集成电路（IC）
公开(公告)号：US07087179B2
公开(公告)日：2006-08-08
申请号：US09734950
申请日：2000-12-11
申请人： Cecilia Y. Mak , John M. White , Kam S. Law , Dan Maydan
发明人： Cecilia Y. Mak , John M. White , Kam S. Law , Dan Maydan
IPC分类号： B29D11/00
CPC分类号： G02B6/12004 , G02B6/13 , G02B6/132
摘要： In one aspect, the invention provides methods and apparatus for forming optical devices on large area substrates. The large area substrates are preferably made of quartz, silica or fused silica. The large area substrates enable larger optical devices to be formed on a single die. In another aspect, the invention provides methods and apparatus for forming integrated optical devices on large area substrates, such as quartz, silica or fused silica substrates. In another aspect, the invention provides methods and apparatus for forming optical devices using damascene techniques on large area substrates or silicon substrates. In another aspect, methods for forming optical devices by bonding an upper cladding layer on a lower cladding and a core is provided.
摘要翻译：一方面，本发明提供了用于在大面积基板上形成光学装置的方法和装置。大面积基板优选由石英，二氧化硅或熔融二氧化硅制成。大面积基板使得能够在单个管芯上形成更大的光学器件。另一方面，本发明提供了用于在大面积衬底（例如石英，二氧化硅或熔融二氧化硅衬底）上形成集成光学器件的方法和装置。在另一方面，本发明提供了使用大面积衬底或硅衬底上的镶嵌技术形成光学器件的方法和装置。在另一方面，提供了通过将下包层和芯上的上包层结合来形成光器件的方法。

6. 发明授权

US5308796A Fabrication of electronic devices by electroless plating of copper onto a metal silicide 失效
标题翻译：通过将铜电镀到金属硅化物上来制造电子器件
公开(公告)号：US5308796A
公开(公告)日：1994-05-03
申请号：US053840
申请日：1993-04-27
申请人： Leonard C. Feldman , Gregg S. Higashi , Cecilia Y. Mak , Barry Miller
发明人： Leonard C. Feldman , Gregg S. Higashi , Cecilia Y. Mak , Barry Miller
IPC分类号： H01L21/28 , C23C18/31 , H01L21/288 , H01L21/768 , H01L23/522 , H01L21/441
CPC分类号： H01L21/288 , H01L21/76879
摘要： It has been found that selective metallization in integrated circuits is expeditiously achieved through a copper plating procedure. In this process, palladium silicide is used as a catalytic surface and an electroless plating bath is employed to introduce copper plating only in regions where the silicide is present. Use of this procedure yields superior filling of vias and windows with excellent conductivity.
摘要翻译：已经发现，通过镀铜工艺快速实现集成电路中的选择性金属化。在该方法中，使用硅化钯作为催化剂表面，并且使用化学镀浴仅在存在硅化物的区域中引入镀铜。使用这种方法可以获得优良的导电性通孔和窗户的填充。

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