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    • 71. 发明申请
    • Network-accessible account system
    • US20050160051A1
    • 2005-07-21
    • US11078354
    • 2005-03-14
    • David Johnson
    • David Johnson
    • H04L9/00
    • G06Q20/10G06Q20/105G06Q20/28G06Q20/3674G06Q20/382G06Q40/00G06Q40/02
    • The present invention is directed to methods of, and systems for, allowing an account participant to add value via a wide-area network to a first account from a second account. A first account server coupled to a wide-area network supports the first account. In a preferred embodiment the wide-area-network-accessible value transfer station (VTS) includes a central processing unit for executing instructions, and a memory unit. The memory unit includes an operating system, software for receiving from a participant via the network a) second account identification information, and b) a value that the participant desires to transfer to the first account from the second account, second account verification software for receiving the second account identification number from said receiving software and for verifying that the second account authorizes the transfer of the specified value, and value transfer software for receiving a value from the receiving software, for receiving a verification from the verification software, and for transferring the specified value to the first account from the second account if the verification is received. The wide-area-network-accessible VTS further includes conductive interconnects connecting the central processing unit and the memory unit to allow portions of the wide-area-network-accessible value transfer station to communicate and to allow the central processing unit to execute the software in the memory unit.
    • 78. 发明授权
    • Method of increasing the bandwidth of a packet bus by reordering reply
packets
    • 通过重新排序应答包来增加分组总线带宽的方法
    • US5006982A
    • 1991-04-09
    • US261047
    • 1988-10-21
    • Ronald J. EbersoleDavid JohnsonDavid BuddeMark S. MyersGerhard Bier
    • Ronald J. EbersoleDavid JohnsonDavid BuddeMark S. MyersGerhard Bier
    • G06F13/42G06F13/36
    • G06F13/4217
    • A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes request-and-reply packets on the bus by determining the use of a next-bus cycle using arbitration, reply deferral, and specification lines and the state of a grant queue and a pipe queue in accordance with a specified protocol. A request is forced to take the next available bus cycle upon the condition that there is an agent identified in the great queue and the pipeline queue is not full. A reply packet is forced to take the next available bus cycle upon the condition that the pipeline queue is full. A reply packet is forced to take the next available bus cycle upon the condition that the grant queue is empty and the pipeline queue is not empty. Giving requests precedence over replies to allows the pipeline to be kept as full as possible. A replying agent assigned to the highest priority slot 1 in the pipeline queue is allowed to defer its own slot in the pipeline queue until a later time to thereby permit a transaction in Slot 2 of the pipeline queue to be completed before the one ahead of it.
    • 一种数据处理器总线,其中通过发出从总线上的代理请求数据的请求分组和返回由请求分组请求的数据的应答分组来传递附加到总线的代理之间的信息。 控制方法通过使用仲裁,回复延迟和规范行以及根据指定协议的授权队列和管道队列的状态来确定使用下一个总线周期来在总线上混合请求和应答分组。 一个请求被强制执行下一个可用的总线周期,条件是在大队列中识别出代理,并且流水线队列未满。 在流水线队列已满的情况下,应答包被强制执行下一个可用的总线周期。 在许可队列为空并且流水线队列不为空的情况下,应答分组被迫采取下一个可用的总线周期。 给予请求优先于回复,以允许管道尽可能保持完整。 分配给流水线队列中的最高优先级时隙1的应答代理被允许推迟其在流水线队列中的其自己的时隙,直到稍后时间,从而允许流水线队列的时隙2中的事务在它之前的一个之前完成 。
    • 79. 发明授权
    • Circuit arrangement with a processor and at least two read-write memories
    • 具有处理器和至少两个读写存储器的电路布置
    • US4800532A
    • 1989-01-24
    • US125628
    • 1987-11-25
    • Karl-Heinz HoneckDavid JohnsonManfred NeugebauerWalter TeutschM. Vittal KiniSteven C. Stacey
    • Karl-Heinz HoneckDavid JohnsonManfred NeugebauerWalter TeutschM. Vittal KiniSteven C. Stacey
    • G11C5/14G11C13/00
    • G11C5/143
    • In order for any failure of the power supply unit for two read-write memories which are operable in parallel, not to result in irreversible damage to data, two parallel power supply circuits are provided for the operation of the memories. Each power supply circuit is capable of supplying the operating current of one of the memories and the standby current of the remaining memory. Each of the power supply circuits in the power supply is buffered with capacitors in such a manner that, upon a fault in one of the power supply circuits, the output voltage, as soon as the capacitive buffer declines from a normal operating voltage to a threshold voltage and to a minimum operating voltage, data secure current reducing steps are taken. The capacitive circuits and threshold voltages are selected such that the period of time the voltage takes to decline from the threshold to the minimum operating voltage is longer than the time required to complete the present read-write operation and to save the relevant data into the memory. One of the memories is then put into standby mode by a monitoring device as the output voltage declines to the threshold voltage leaving only one active memory which can be operated from one of the two memory power supply circuits.
    • 为了并联可操作的两个读写存储器的电源单元的任何故障,不会对数据造成不可逆的损坏,因此为存储器的操作提供两个并联电源电路。 每个电源电路能够提供其中一个存储器的工作电流和剩余存储器的待机电流。 电源中的每个电源电路用电容器缓冲,使得当电源电路中的一个故障时,输出电压一旦电容缓冲器从正常工作电压下降到阈值 电压和最小工作电压,采取数据安全电流降低步骤。 选择电容电路和阈值电压使得电压从阈值下降到最小工作电压的时间段长于完成当前读写操作所需的时间并将相关数据保存到存储器中 。 其中一个存储器随后随着输出电压下降到阈值电压而被置于待机模式,只剩下一个可从两个存储器电源电路之一操作的有效存储器。