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1. 发明授权

US5006982A Method of increasing the bandwidth of a packet bus by reordering reply packets 失效
标题翻译：通过重新排序应答包来增加分组总线带宽的方法
公开(公告)号：US5006982A
公开(公告)日：1991-04-09
申请号：US261047
申请日：1988-10-21
申请人： Ronald J. Ebersole , David Johnson , David Budde , Mark S. Myers , Gerhard Bier
发明人： Ronald J. Ebersole , David Johnson , David Budde , Mark S. Myers , Gerhard Bier
IPC分类号： G06F13/42 , G06F13/36
CPC分类号： G06F13/4217
摘要： A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes request-and-reply packets on the bus by determining the use of a next-bus cycle using arbitration, reply deferral, and specification lines and the state of a grant queue and a pipe queue in accordance with a specified protocol. A request is forced to take the next available bus cycle upon the condition that there is an agent identified in the great queue and the pipeline queue is not full. A reply packet is forced to take the next available bus cycle upon the condition that the pipeline queue is full. A reply packet is forced to take the next available bus cycle upon the condition that the grant queue is empty and the pipeline queue is not empty. Giving requests precedence over replies to allows the pipeline to be kept as full as possible. A replying agent assigned to the highest priority slot 1 in the pipeline queue is allowed to defer its own slot in the pipeline queue until a later time to thereby permit a transaction in Slot 2 of the pipeline queue to be completed before the one ahead of it.
摘要翻译：一种数据处理器总线，其中通过发出从总线上的代理请求数据的请求分组和返回由请求分组请求的数据的应答分组来传递附加到总线的代理之间的信息。控制方法通过使用仲裁，回复延迟和规范行以及根据指定协议的授权队列和管道队列的状态来确定使用下一个总线周期来在总线上混合请求和应答分组。一个请求被强制执行下一个可用的总线周期，条件是在大队列中识别出代理，并且流水线队列未满。在流水线队列已满的情况下，应答包被强制执行下一个可用的总线周期。在许可队列为空并且流水线队列不为空的情况下，应答分组被迫采取下一个可用的总线周期。给予请求优先于回复，以允许管道尽可能保持完整。分配给流水线队列中的最高优先级时隙1的应答代理被允许推迟其在流水线队列中的其自己的时隙，直到稍后时间，从而允许流水线队列的时隙2中的事务在它之前的一个之前完成。

2. 发明授权

US4975831A High-availability computer system with a predefinable configuration of the modules 失效
标题翻译：高可用性计算机系统具有模块的预定义配置
公开(公告)号：US4975831A
公开(公告)日：1990-12-04
申请号：US191629
申请日：1988-05-09
申请人： Sven-Axel Nilsson , David Budde
发明人： Sven-Axel Nilsson , David Budde
IPC分类号： G06F11/00 , G06F15/177
CPC分类号： G06F15/177 , G06F11/006
摘要： A computer system operative during an initialization phase to initialize modules of the system and during a subsequent non-initialization phase to transfer information between the initialized modules. A module bus (MB) has 32 signal lines beginning with a least-significant-bit signal line and ending with a most-significant-bit signal line. The bus (MB) connects the modules for data transfers after the initialization phase over bidirectional address lines and data lines connected to the module bus. A system support module (SSMI) starts the initialization phase by energizing an initialization signal line (INIT). In response, a processor (GDP) generates identification command information over the bus (MB) that continas a first data record and a second data record. The first data record is comprised of bits equal to the number of signal lines in the 32-bit module bus, with only one logical one in the first data field, the position of the logical one advancing consecutively from the least significant bit position to the most significant bit position for each successive identification command generated by the processor. The second data record is an identification code uniquely identifying the one of the modules activated by the first record to receive the second record and hence its identification code.
摘要翻译：在初始化阶段期间操作以初始化系统的模块并且在随后的非初始化阶段期间在初始化模块之间传送信息的计算机系统。模块总线（MB）具有从最低有效位信号线开始并以最高有效位信号线结束的32条信号线。总线（MB）通过双向地址线和连接到模块总线的数据线在初始化阶段之后连接用于数据传输的模块。系统支持模块（SSMI）通过激励初始化信号线（INIT）来启动初始化阶段。作为响应，处理器（GDP）通过连接第一数据记录和第二数据记录的总线（MB）产生识别命令信息。第一数据记录包括等于32位模块总线中的信号线数量的位，在第一数据字段中只有一个逻辑1，逻辑1的位置从最低有效位位置连续地前进到由处理器生成的每个连续识别命令的最高有效位位置。第二数据记录是唯一地识别由第一记录激活以接收第二记录并因此识别代码的模块中的一个模块的识别码。

3. 发明授权

US4891753A Register scorboarding on a microprocessor chip 失效
标题翻译：在微处理器芯片上注册scorboarding
公开(公告)号：US4891753A
公开(公告)日：1990-01-02
申请号：US935193
申请日：1986-11-26
申请人： David Budde , Robert Riches , Michael T. Imel , Glen Myers , Konrad Lai
发明人： David Budde , Robert Riches , Michael T. Imel , Glen Myers , Konrad Lai
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
CPC分类号： G06F9/3838 , G06F9/3836
摘要： When a load instruction is encountered, a read operation is sent to the bus control logic, the register is marked as busy, and execution proceeds to the next instruction. When an instruction is executed, it proceeds providing that its source and destination registers are not marked busy; otherwise the instruction is retried. When data are returned as the result of a read operation, the destination register(s) are marked as not busy.
摘要翻译：当遇到加载指令时，读操作被发送到总线控制逻辑，寄存器被标记为忙，并且执行进行到下一条指令。当执行指令时，继续执行其源和目标寄存器未标记为忙; 否则将重试该指令。当作为读取操作的结果返回数据时，目标寄存器被标记为不忙。

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