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71. 发明授权

US06304098B1 Method and apparatus for reducing noise in communication channels having a shared reference signal 有权
标题翻译：具有共享参考信号的通信信道中降低噪声的方法和装置
公开(公告)号：US06304098B1
公开(公告)日：2001-10-16
申请号：US09524683
申请日：2000-03-14
申请人： Robert J. Drost , Neil C. Wilhelm
发明人： Robert J. Drost , Neil C. Wilhelm
IPC分类号： H03K19003
CPC分类号： H04L5/20 , H04L25/085
摘要： Method and circuitry for improving noise immunity of differential data channels that use a shared reference channel by substantially matching their respective noise transfer functions. Any combination of various circuit parameters at the reference channel including termination resistance R, channel impedance Zo, and parasitic inductance L are scaled to substantially match the noise transfer function of the reference channel to that of the data channels.
摘要翻译：用于通过基本上匹配它们各自的噪声传递函数来提高使用共享参考信道的差分数据信道的抗噪声性的方法和电路。包括终端电阻R，通道阻抗Zo和寄生电感L在内的参考通道的各种电路参数的任何组合被缩放以使得参考通道的噪声传递函数与数据通道的噪声传递函数基本一致。

72. 发明授权

US06194929B1 Delay locking using multiple control signals 失效
标题翻译：使用多个控制信号延迟锁定
公开(公告)号：US06194929B1
公开(公告)日：2001-02-27
申请号：US08883525
申请日：1997-06-25
申请人： Robert J. Drost , Jose M. Cruz , Robert J. Bosnyak
发明人： Robert J. Drost , Jose M. Cruz , Robert J. Bosnyak
IPC分类号： H03L706
CPC分类号： H03L7/0812 , H03L7/0893 , H03L7/0896
摘要： A delay-locked loop includes a phase detection circuit, a charge pump circuit and a phase shift circuit. The phase detection circuit is coupled to receive a first signal and a second signal. The phase detection circuit generates a phase-error output signal indicative of whether the first signal is ahead of or behind the second signal in phase responsive to receiving the first and second signals. The charge pump circuit is coupled to receive a phase-error signal derived from the phase-error output signal. The charge pump circuit generates a plurality of control output signals. Each of the control output signals are based upon the phase-error signal and by at least one signal derived from one other of the control output signals. The phase shift circuit is coupled to receive a plurality of control input signals and a plurality of periodic input signals. The control input signals are derived from the control output signals. Each of the periodic input signals have a different phase. The phase shift circuit applying the control input signals to select from among the periodic input signals to generate a periodic output signal. The periodic output signal being one of the first and second signals.
摘要翻译：延迟锁定环包括相位检测电路，电荷泵电路和相移电路。相位检测电路被耦合以接收第一信号和第二信号。相位检测电路响应于接收到第一和第二信号而产生指示第一信号是否在相位之前或之后的第二信号的相位误差输出信号。电荷泵电路被耦合以接收从相位误差输出信号导出的相位误差信号。电荷泵电路产生多个控制输出信号。每个控制输出信号基于相位误差信号和由控制输出信号中的另一个导出的至少一个信号。相移电路被耦合以接收多个控制输入信号和多个周期性输入信号。控制输入信号由控制输出信号导出。每个周期性输入信号具有不同的相位。相移电路施加控制输入信号以从周期性输入信号中选择以产生周期性输出信号。周期性输出信号是第一和第二信号之一。

73. 发明授权

US5955911A On-chip differential resistance technique with noise immunity and symmetric resistance 失效
标题翻译：具有抗噪声和对称电阻的片上差分电阻技术
公开(公告)号：US5955911A
公开(公告)日：1999-09-21
申请号：US944141
申请日：1997-10-06
申请人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
发明人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
IPC分类号： H03H11/24 , H03H11/28 , H03K17/62 , H03L5/00
CPC分类号： H03H11/28 , H03H11/24
摘要： An on-chip resistance to an input current of an input signal includes a parallel transistor resistor and a control circuit for biasing the transistors of the parallel transistor resistor. The parallel transistor resistor includes first and second transistors of first and second types. Each transistor includes first and second current handling terminals and a control terminal. The control terminals are coupled to receive control signals from the control circuit. The first current handling terminals are coupled to provide an input node for receiving an input signal, and the second current handling terminals are coupled to provide an output signal. The control circuit is coupled to provide the first and second control signals for biasing the respective first and second transistors so that a first derivative of a resistance of the parallel transistor resistor in relation to an input-to-output voltage is zero at a selectable operation point.
摘要翻译：对输入信号的输入电流的片上电阻包括并联晶体管电阻器和用于偏置并联晶体管电阻器的晶体管的控制电路。并联晶体管电阻器包括第一和第二类型的第一和第二晶体管。每个晶体管包括第一和第二电流处理终端和控制终端。控制端子被耦合以从控制电路接收控制信号。第一当前处理终端被耦合以提供用于接收输入信号的输入节点，并且第二电流处理终端被耦合以提供输出信号。控制电路被耦合以提供用于偏置相应的第一和第二晶体管的第一和第二控制信号，使得并行晶体管电阻器的电阻相对于输入到输出电压的一阶导数在可选择的操作时为零点。

74. 发明授权

US5905399A CMOS integrated circuit regulator for reducing power supply noise 失效
标题翻译： CMOS集成电路调节器，用于降低电源噪声
公开(公告)号：US5905399A
公开(公告)日：1999-05-18
申请号：US885598
申请日：1997-06-30
申请人： Robert J. Bosnyak , Robert J. Drost
发明人： Robert J. Bosnyak , Robert J. Drost
IPC分类号： H01L21/8238 , G05F1/46 , H01L27/092 , H03K17/16 , H03K19/00
CPC分类号： G05F1/467
摘要： A CMOS integrated circuit regulator for mixed mode integrated circuits reduces digital switching noise through use of a clamped dual source follower circuit and a charge reservoir bypass capacitor. Relatively constant current is provided to the CMOS logic during transitions to minimize switching noise.
摘要翻译：用于混合模式集成电路的CMOS集成电路调节器通过使用钳位双源继电器电路和电荷储存器旁路电容来降低数字开关噪声。在转换期间向CMOS逻辑提供相对恒定的电流以最小化开关噪声。

75. 发明授权

US5767699A Fully complementary differential output driver for high speed digital communications 失效
标题翻译：用于高速数字通信的完全互补的差分输出驱动器
公开(公告)号：US5767699A
公开(公告)日：1998-06-16
申请号：US653788
申请日：1996-05-28
申请人： Robert J. Bosnyak , Robert J. Drost , David M. Murata
发明人： Robert J. Bosnyak , Robert J. Drost , David M. Murata
IPC分类号： H04L25/02 , H03K19/0185
CPC分类号： H04L25/0272 , H04L25/0298 , H04L25/028
摘要： A terminating element is connected between the terminating ends of a transmission line pair. A switching mechanism coupled to the originating ends of the transmission line pair steers a constant current through the transmission line pair. In response to input control signals, the switching mechanism steers the constant current in a complementary fashion into one of the lines of the transmission lines pair to creates a differential output voltage across the terminating element. Controlling the differential voltage by manipulating current flow allows for acurate control over V.sub.OH and V.sub.OL levels. Since the terminating element is connected between terminating ends of the transmission line pair, nearly all of the constant current flowing the driver contributes to the differential output voltage, thereby reducing power undesirable power dissipation. Further, the alternating current flow through the transmission line pair creates a virtual ground at the center of the terminating element and thereby allows drivers in accordance with the present invention to obtain twice the output voltage swing of conventional transmission line drivers without requiring additional current. In this manner, a further reduction in power consumption is achieved.
摘要翻译：终端元件连接在传输线对的终端之间。耦合到传输线对的起始端的切换机构引导通过传输线对的恒定电流。响应于输入控制信号，开关机构以互补方式将恒定电流引导到传输线对中的一条线路中，以在端接元件两端产生差分输出电压。通过操纵电流控制差分电压可以对VOH和VOL电平进行精确的控制。由于端接元件连接在传输线对的终端之间，所以流过驱动器的几乎所有的恒定电流有助于差分输出电压，从而减少功率不期望的功耗。此外，通过传输线对的交流电流在终端元件的中心处产生虚拟接地，从而允许根据本发明的驱动器获得传统传输线驱动器的输出电压摆动的两倍而不需要额外的电流。以这种方式，实现了功率消耗的进一步降低。

76. 发明授权

US08482072B2 Semiconductor die with integrated electro-static discharge device 有权
标题翻译：具有集成静电放电装置的半导体芯片
公开(公告)号：US08482072B2
公开(公告)日：2013-07-09
申请号：US13473479
申请日：2012-05-16
申请人： Robert J. Drost , Robert D. Hopkins , Alex Chow
发明人： Robert J. Drost , Robert D. Hopkins , Alex Chow
IPC分类号： H01L23/62 , H01L29/72 , H01L29/74 , H01L31/111 , H01L29/73
CPC分类号： H01L23/60 , H01L24/05 , H01L27/0288 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.
摘要翻译：描述半导体管芯。该半导体管芯包括具有耦合到输入 - 输出（I / O）焊盘的金属部件并且经由信号线耦合到接地电压的静电放电（ESD）器件。此外，金属部件和I / O焊盘的相邻边缘分开限定ESD间隙的间隔。当场发射或电离电流流过ESD间隙时，金属部件为瞬态ESD信号提供到接地电压的放电路径。此外，ESD间隙至少部分封闭，使得在ESD间隙中存在气体。

77. 发明授权

US08299839B2 Capacitively and conductively coupled multiplexer 有权
标题翻译：电容和导通耦合多路复用器
公开(公告)号：US08299839B2
公开(公告)日：2012-10-30
申请号：US12352481
申请日：2009-01-12
申请人： Robert J. Drost , Alex Chow , Robert D. Hopkins
发明人： Robert J. Drost , Alex Chow , Robert D. Hopkins
IPC分类号： H03K17/00
CPC分类号： H03K17/005 , H03K17/693
摘要： A capacitively and conductively coupled multiplexer (C3mux) circuit is described. This C3mux circuit includes a set of nonlinear coupling capacitors, such as metal-oxide-semiconductor (MOS) transistors, that can multiplex multiple input signals while minimizing the parasitic capacitance penalty associated with the ‘off’ paths. In particular, the capacitance of a given MOS transistor depends on whether its channel is present or absent. Furthermore, this channel is formed based on whether the gate-to-source and drain voltages for the MOS transistor are greater than the MOS transistor's threshold voltage. Note that the capacitance of the MOS transistors in the C3mux circuit is low for the unselected inputs. Consequently, the parasitic loading and the delay increase slowly as a function of the number of inputs. Moreover, the conductive feedback can be used to maintain a DC level of the input signals.
摘要翻译：描述了电容和导电耦合多路复用器（C3mux）电路。该C3mux电路包括一组非线性耦合电容器，例如金属氧化物半导体（MOS）晶体管，其可以复用多个输入信号，同时最小化与关闭路径相关联的寄生电容损耗。特别地，给定MOS晶体管的电容取决于其通道是存在还是不存在。此外，该沟道是基于MOS晶体管的栅极 - 源极和漏极电压是否大于MOS晶体管的阈值电压而形成的。请注意，C3mux电路中的MOS晶体管的电容对于未选择的输入为低电平。因此，寄生负载和延迟作为输入数量的函数缓慢增加。此外，导电反馈可用于维持输入信号的直流电平。

78. 发明授权

US08164918B2 Steering fabric that facilitates reducing power use for proximity communication 有权
标题翻译：有助于减少接近通讯用电的转向结构
公开(公告)号：US08164918B2
公开(公告)日：2012-04-24
申请号：US12317659
申请日：2008-12-24
申请人： Alex Chow , Robert J. Drost , Ronald Ho , Robert Proebsting , Arlene Proebsting, legal representative
发明人： Alex Chow , Robert J. Drost , Ronald Ho , Robert Proebsting
IPC分类号： H05K7/00
CPC分类号： H01L23/48 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit signals using proximity communication. This array is comprised of a set of macropads, where each given macropad is comprised of a set of micropads that can be configured to transmit a signal. A steering fabric routes signals to and within macropads, such that a subset of the micropads in the array can be configured to transmit the signal to a receiving component. Each macropad receives a limited number of input signals, with the steering fabric routing input signals to the micropads of the macropads. By limiting the number of input signals that are routed to the micropads of the macropads, the steering fabric eliminates redundant steering configurations for the array and reduces the power needed to transmit the signal.
摘要翻译：本发明的一个实施例提供一种有助于减少邻近通信所需的功率的系统。该系统包括具有使用接近通信传输信号的传输焊盘阵列的集成电路。该阵列由一组宏阵列组成，其中每个给定的宏阵列由可配置为传输信号的一组微阵列组成。导向结构将信号路由到宏区域内并且在宏阵列内传送，使得阵列中的微阵列的子集可以被配置为将信号发送到接收组件。每个macropad都接收到有限数量的输入信号，其中转向结构将输入信号输入到macropads的微型麦克风。通过限制输入信号的数量，路由到巨型阵列的微阵列，转向结构消除了阵列的冗余转向配置，并减少传输信号所需的功率。

79. 发明授权

US08150266B1 Method and apparatus for performing butterfly differential signaling 有权
标题翻译：用于执行蝶差分信令的方法和装置
公开(公告)号：US08150266B1
公开(公告)日：2012-04-03
申请号：US10660861
申请日：2003-09-12
申请人： Robert J. Drost
发明人： Robert J. Drost
IPC分类号： H04B10/00 , H04B3/28
CPC分类号： H04B10/801 , H04B3/28
摘要： One embodiment of the present invention provides a system that performs differential signaling through parallel ports in a manner that reduces noise caused by coupling between neighboring ports. The system includes parallel ports for transmitting differential signals from a sender to a receiver, wherein the parallel ports are organized in a two-dimensional grid. Each differential signal is transmitted through a first port and a second port that carry complementary positive and negative components of the differential signal. The first and second ports of a differential pair are diagonally adjacent to each other in the two-dimensional grid. Because the first and second ports transition in opposite directions, coupling noise is cancelled on a neighboring port that is horizontally adjacent to the first port and vertically adjacent to the second port. Moreover, a transition on the neighboring port couples equally to the first port and second port and is consequently rejected as common-mode noise by a corresponding differential receiver.
摘要翻译：本发明的一个实施例提供一种以减少由相邻端口之间的耦合引起的噪声的方式通过并行端口执行差分信令的系统。该系统包括用于从发送器到接收器发送差分信号的并行端口，其中并行端口被组织成二维网格。每个差分信号通过携带差分信号的互补正和负分量的第一端口和第二端口传输。差分对的第一和第二端口在二维栅格中彼此对角地相邻。因为第一和第二端口在相反方向上转变，所以耦合噪声在与第一端口水平相邻并且与第二端口垂直相邻的相邻端口上被消除。此外，相邻端口上的转换同样地耦合到第一端口和第二端口，并且因此被相应的差分接收机拒绝为共模噪声。

80. 发明申请

US20110261637A1 INCREASED DRAM-ARRAY THROUGHPUT USING INACTIVE BITLINES 有权
标题翻译：通过使用不活泼的BITLINES来增加DRAM-ARRAY
公开(公告)号：US20110261637A1
公开(公告)日：2011-10-27
申请号：US13082785
申请日：2011-04-08
申请人： Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
发明人： Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C7/1048 , G11C11/4096 , G11C2207/002
摘要： A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel, as opposed to a proximate I/O line that is in use. For example, unused bitlines located on the top and bottom of the memory array may be used to route data signals to adjacent local I/O lines. In particular, the data signals can be placed on unused local I/O lines which are associated with adjacent bitline sense amplifiers. The resulting increased communication bandwidth can overcome the constraints imposed by the limited number of local I/O lines in the memory device without appreciably increasing the chip size, power consumption, or cost.
摘要翻译：描述了具有增加的通信带宽的存储器件。在该存储器件中，控制逻辑响应于读取命令，使用不活动位线从存储器阵列路由数据信号。然后将这些数据信号放置在相邻的未使用的输入/输出（I / O）线路或路由通道上，而不是正在使用的近似I / O线。例如，位于存储器阵列的顶部和底部的未使用的位线可以用于将数据信号路由到相邻的本地I / O线路。特别地，数据信号可以放置在与相邻位线读出放大器相关联的未使用的本地I / O线上。所产生的增加的通信带宽可以克服由有限数量的本地I / O线在存储器件中施加的约束，而不会明显增加芯片尺寸，功耗或成本。

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