专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6031406A Single rail regulator 失效
标题翻译：单轨调节器
公开(公告)号：US6031406A
公开(公告)日：2000-02-29
申请号：US883524
申请日：1997-06-26
申请人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
发明人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
IPC分类号： H01L27/02 , H03K5/00
CPC分类号： H01L27/0207
摘要： An apparatus for suppressing the effect of noise from a first circuit on the performance of a second circuit wherein the first and second circuits are on a common substrate. Each of the first and second circuits include first and second supply rails. The apparatus includes a noise isolation circuit and a noise transference circuit. The noise isolation circuit is for coupling the first supply rails of the first and second circuits to prevent noise on the first supply rail of the first circuit from transferring to the first supply rail of the second circuit. The noise transference circuit is for coupling the second supply rails of the first and second circuits so that noise on the second supply rail of the first circuit is transferred to the second supply rail of the second circuit.
摘要翻译：一种用于抑制来自第一电路的噪声对第二电路的性能的影响的装置，其中第一和第二电路在公共衬底上。第一和第二电路中的每一个包括第一和第二电源轨。该装置包括噪声隔离电路和噪声转移电路。噪声隔离电路用于耦合第一和第二电路的第一电源轨，以防止第一电路的第一电源轨上的噪声转移到第二电路的第一电源轨。噪声转移电路用于耦合第一和第二电路的第二电源轨，使得第一电路的第二电源轨上的噪声被传送到第二电路的第二电源轨。

2. 发明授权

US6084452A Clock duty cycle control technique 失效
标题翻译：时钟占空比控制技术
公开(公告)号：US6084452A
公开(公告)日：2000-07-04
申请号：US107898
申请日：1998-06-30
申请人： Robert J. Drost , Jose M. Cruz , Robert J. Bosnyak
发明人： Robert J. Drost , Jose M. Cruz , Robert J. Bosnyak
IPC分类号： H03K5/156 , H03K3/017
CPC分类号： H03K5/1565
摘要： An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes a reference circuit and a comparison circuit. The reference circuit is coupled to a first node having the first voltage and a second node having the second voltage to generate a reference signal from the first and second voltages. The reference circuit includes at least one instance of a first electrical characteristic cell. The comparison circuit is coupled to receive a feedback clock signal and to generate a comparison signal therefrom. The comparison circuit includes at least one instance of the first electrical characteristic cell. The duty cycle error measurement circuit is coupled to receive the reference signal and the comparison signal. The duty cycle error measurement circuit rejects the common mode of the reference and comparison signals and passes the differential mode of the reference and comparison signals to generate a duty cycle adjust signal responsive to receiving the reference and comparison signals. The duty cycle adjuster is coupled to receive an input clock signal and the duty cycle adjust signal and to provide the single-ended clock signal. The single-ended clock signal has a duty cycle determined at least in part by the duty cycle adjust signal.
摘要翻译：一个装置调整单端时钟信号的占空比。单端时钟信号在第一和第二电压之间振荡。该装置包括误差指示电路，占空比误差测量电路和占空比调节器。误差指示电路包括参考电路和比较电路。参考电路耦合到具有第一电压的第一节点和具有第二电压的第二节点以从第一和第二电压产生参考信号。参考电路包括第一电特征单元的至少一个实例。比较电路被耦合以接收反馈时钟信号并从其产生比较信号。比较电路包括第一电特征单元的至少一个实例。负载周期误差测量电路被耦合以接收参考信号和比较信号。占空比误差测量电路拒绝参考和比较信号的共模，并通过参考和比较信号的差分模式，以响应于接收参考和比较信号产生占空比调整信号。负载周期调节器被耦合以接收输入时钟信号和占空比调整信号并提供单端时钟信号。单端时钟信号具有至少部分由占空比调整信号确定的占空比。

3. 发明授权

US6016082A Low phase noise LC oscillator for microprocessor clock distribution 失效
标题翻译：用于微处理器时钟分配的低相位噪声LC振荡器
公开(公告)号：US6016082A
公开(公告)日：2000-01-18
申请号：US23360
申请日：1998-02-13
申请人： Jose M. Cruz , Robert J. Bosnyak , Robert J. Drost
发明人： Jose M. Cruz , Robert J. Bosnyak , Robert J. Drost
IPC分类号： H03B1/00 , H03B5/12 , H03L7/093 , H03L7/099 , H03L7/183 , H03B5/18
CPC分类号： H03L7/183 , H03B5/1215 , H03B5/1228 , H03B5/1271 , H03L7/093 , H03L7/099 , H03B2201/0208
摘要： A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In addition, the LC oscillator is operable over a range of frequencies sufficient to support both normal full power operation, and reduced power operation of the microprocessor. The LC oscillator minimizes clock jitter problems and so permits extension of the microprocessor operating frequency to even higher levels than heretofore were possible. An output signal from a phase-frequency detector is a frequency control signal on a frequency control input line of a level converter and filter circuit of the LC oscillator. The output signal from level converter and filter circuit is a filtered frequency control signal on a control voltage input line to a continuously modifiable gigahertz frequency voltage controlled oscillator (VCO) circuit. Continuously modifiable gigahertz frequency VCO circuit generates an output signal with a frequency that is dependent on the voltage on control voltage input line. The output signal from the continuously modifiable gigahertz frequency VCO is a differential current signal to a level shifter output circuit. The level shifter output circuit converts the current signal to a single-ended voltage that is supplied to an output driver. The output driver provides the output signal to a clock distribution network.
摘要翻译：微处理器包括片上低相位噪声CMOS LC电容振荡器。 LC振荡器对电源波动相对不敏感。此外，LC振荡器可以在足以支持正常全功率操作和微处理器的功率操作的减少的频率范围内操作。 LC振荡器使时钟抖动问题最小化，因此允许将微处理器工作频率扩展到甚至比以前更高的水平。来自相位频率检测器的输出信号是LC振荡器的电平转换器和滤波器电路的频率控制输入线上的频率控制信号。来自电平转换器和滤波器电路的输出信号是在可连续修改的千兆赫兹频率压控振荡器（VCO）电路的控制电压输入线上的滤波频率控制信号。连续可修改的千兆赫兹频率VCO电路产生的输出信号的频率取决于控制电压输入线上的电压。来自连续可修改的千兆赫兹频率VCO的输出信号是到电平移位器输出电路的差分电流信号。电平移位器输出电路将电流信号转换为提供给输出驱动器的单端电压。输出驱动器将输出信号提供给时钟分配网络。

4. 发明授权

US06526552B1 Long line receiver for CMOS integrated circuits 有权
标题翻译：用于CMOS集成电路的长线接收器
公开(公告)号：US06526552B1
公开(公告)日：2003-02-25
申请号：US09696451
申请日：2000-10-25
申请人： Robert J. Bosnyak , Jose M. Cruz , Robert J. Drost
发明人： Robert J. Bosnyak , Jose M. Cruz , Robert J. Drost
IPC分类号： G06F945
CPC分类号： H04L25/0292 , H03K5/086
摘要： A clamping circuit which is connected to each long line, preferably adjacent the receiver. The clamping circuit biases the long line at the trigger threshold of the receiver. Thus, instead of amplifying the signal as a repeater will do, the present invention clamps the line to the threshold, thus allowing a faster response since the line doesn't have to be charged or discharged from a lower or higher level to the threshold. This thus speeds up the transition at the receiver without requiring a repeater or a keeper.
摘要翻译：钳位电路，其连接到每个长线，优选地邻近接收器。钳位电路在接收器的触发阈值处偏置长线。因此，代替放大作为中继器的信号，本发明将线路钳位到阈值，从而允许更快的响应，因为线路不必从较低或更高的电平被充电或放电到阈值。这样就加快了接收机的转换，而不需要中继器或保持器。

5. 发明授权

US06373304B1 Techniques for making and using an improved loop filter which maintains a constant zero frequency to bandwidth ratio 失效
标题翻译：制造和使用改进的环路滤波器的技术，其保持恒定的零频率到带宽比
公开(公告)号：US06373304B1
公开(公告)日：2002-04-16
申请号：US08938932
申请日：1997-10-02
申请人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
发明人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
IPC分类号： H03K500
CPC分类号： H03L7/093
摘要： An improved loop filter contains an active device which maintains a phase lock loop's zero frequency to bandwidth ratio substantially constant with changes in the incoming frequency. It does this by maintaining filter resistance proportional to the inverse square root of the filter current, and without requiring duplicates of circuit elements. Constructed in this way a phase lock loop can be achieved which has a wide operating frequency range and low tracking jitter.
摘要翻译：改进的环路滤波器包含一个有源器件，它通过输入频率的变化使锁相环的零频率与带宽比基本恒定。它通过保持滤波器电阻与滤波器电流的反平方根成比例，并且不需要电路元件的重复来实现。以这种方式构造，可以实现具有宽工作频率范围和低跟踪抖动的锁相环。

6. 发明授权

US5912567A Dual differential comparator with weak equalization and narrow metastability region 失效
标题翻译：具有弱均衡和窄亚稳态区域的双差分比较器
公开(公告)号：US5912567A
公开(公告)日：1999-06-15
申请号：US956183
申请日：1997-10-22
申请人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
发明人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： In a sample-and-hold circuit, an input is tracked at an output during a tracking period and the input is held during an holding period, the tracking period and holding period defined by a clock signal input to the sample-and-hold circuit, wherein the output is a differential output having a positive output node and a negative output node with the output signal represented by a voltage difference from the negative output node to the positive output node. During the tracking period, an equalizing transistor between the output nodes is turned on to bring the output to a common mode level for the output. During the holding period, the equalizing transistor is turned off and a regenerative circuit drives the output nodes apart, thus amplifying the input signal.
摘要翻译：在采样和保持电路中，在跟踪周期期间，在输出端跟踪输入，并且在保持周期期间保持输入，由输入到采样和保持电路的时钟信号定义的跟踪周期和保持周期，其中所述输出是具有正输出节点和所述输出信号的负输出节点的差分输出，所述输出信号由从所述负输出节点到所述正输出节点的电压差表示。在跟踪期间，输出节点之间的均衡晶体管导通，使输出达到输出的共模电平。在保持期间，均衡晶体管截止，再生电路将输出节点分开驱动，从而放大输入信号。

7. 发明授权

US06194929B1 Delay locking using multiple control signals 失效
标题翻译：使用多个控制信号延迟锁定
公开(公告)号：US06194929B1
公开(公告)日：2001-02-27
申请号：US08883525
申请日：1997-06-25
申请人： Robert J. Drost , Jose M. Cruz , Robert J. Bosnyak
发明人： Robert J. Drost , Jose M. Cruz , Robert J. Bosnyak
IPC分类号： H03L706
CPC分类号： H03L7/0812 , H03L7/0893 , H03L7/0896
摘要： A delay-locked loop includes a phase detection circuit, a charge pump circuit and a phase shift circuit. The phase detection circuit is coupled to receive a first signal and a second signal. The phase detection circuit generates a phase-error output signal indicative of whether the first signal is ahead of or behind the second signal in phase responsive to receiving the first and second signals. The charge pump circuit is coupled to receive a phase-error signal derived from the phase-error output signal. The charge pump circuit generates a plurality of control output signals. Each of the control output signals are based upon the phase-error signal and by at least one signal derived from one other of the control output signals. The phase shift circuit is coupled to receive a plurality of control input signals and a plurality of periodic input signals. The control input signals are derived from the control output signals. Each of the periodic input signals have a different phase. The phase shift circuit applying the control input signals to select from among the periodic input signals to generate a periodic output signal. The periodic output signal being one of the first and second signals.
摘要翻译：延迟锁定环包括相位检测电路，电荷泵电路和相移电路。相位检测电路被耦合以接收第一信号和第二信号。相位检测电路响应于接收到第一和第二信号而产生指示第一信号是否在相位之前或之后的第二信号的相位误差输出信号。电荷泵电路被耦合以接收从相位误差输出信号导出的相位误差信号。电荷泵电路产生多个控制输出信号。每个控制输出信号基于相位误差信号和由控制输出信号中的另一个导出的至少一个信号。相移电路被耦合以接收多个控制输入信号和多个周期性输入信号。控制输入信号由控制输出信号导出。每个周期性输入信号具有不同的相位。相移电路施加控制输入信号以从周期性输入信号中选择以产生周期性输出信号。周期性输出信号是第一和第二信号之一。

8. 发明授权

US5955911A On-chip differential resistance technique with noise immunity and symmetric resistance 失效
标题翻译：具有抗噪声和对称电阻的片上差分电阻技术
公开(公告)号：US5955911A
公开(公告)日：1999-09-21
申请号：US944141
申请日：1997-10-06
申请人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
发明人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
IPC分类号： H03H11/24 , H03H11/28 , H03K17/62 , H03L5/00
CPC分类号： H03H11/28 , H03H11/24
摘要： An on-chip resistance to an input current of an input signal includes a parallel transistor resistor and a control circuit for biasing the transistors of the parallel transistor resistor. The parallel transistor resistor includes first and second transistors of first and second types. Each transistor includes first and second current handling terminals and a control terminal. The control terminals are coupled to receive control signals from the control circuit. The first current handling terminals are coupled to provide an input node for receiving an input signal, and the second current handling terminals are coupled to provide an output signal. The control circuit is coupled to provide the first and second control signals for biasing the respective first and second transistors so that a first derivative of a resistance of the parallel transistor resistor in relation to an input-to-output voltage is zero at a selectable operation point.
摘要翻译：对输入信号的输入电流的片上电阻包括并联晶体管电阻器和用于偏置并联晶体管电阻器的晶体管的控制电路。并联晶体管电阻器包括第一和第二类型的第一和第二晶体管。每个晶体管包括第一和第二电流处理终端和控制终端。控制端子被耦合以从控制电路接收控制信号。第一当前处理终端被耦合以提供用于接收输入信号的输入节点，并且第二电流处理终端被耦合以提供输出信号。控制电路被耦合以提供用于偏置相应的第一和第二晶体管的第一和第二控制信号，使得并行晶体管电阻器的电阻相对于输入到输出电压的一阶导数在可选择的操作时为零点。

9. 发明授权

US06414538B1 Circuit to reduce AC component of bias currents in high speed transistor logic circuits 有权
标题翻译：降低高速晶体管逻辑电路中偏置电流的交流分量的电路
公开(公告)号：US06414538B1
公开(公告)日：2002-07-02
申请号：US09680673
申请日：2000-10-06
申请人： Robert J. Bosnyak , Jose M. Cruz
发明人： Robert J. Bosnyak , Jose M. Cruz
IPC分类号： G05F302
CPC分类号： G05F3/205
摘要： A low-pass filter to filter the internal bias voltages. It is connected locally at the bias voltage input of each bias current source the low-pass filter reduces the AC overshoot oscillations of a local bias voltage generated by the bias voltage generator upon a changing in the amount of current sourced by other current sources. A single bias voltage generator is connected to a bias voltage input of a number of bias current sources. Each current source has a low pass filter to filter the bias voltage.
摘要翻译：低通滤波器来滤除内部偏置电压。它在每个偏置电流源的偏置电压输入端局部连接，低通滤波器减少由偏置电压发生器产生的局部偏置电压的交流过冲振荡，这是由于其他电流源的电流量的变化。单个偏置电压发生器连接到多个偏置电流源的偏置电压输入端。每个电流源都有一个低通滤波器来滤除偏置电压。

10. 发明授权

US06396316B1 Clock buffer with LC circuit for jitter reduction 有权
标题翻译：具有LC电路的时钟缓冲器，用于抖动降低
公开(公告)号：US06396316B1
公开(公告)日：2002-05-28
申请号：US09667060
申请日：2000-09-21
申请人： Jose M. Cruz , Robert J. Bosnyak
发明人： Jose M. Cruz , Robert J. Bosnyak
IPC分类号： H03B100
CPC分类号： H03K19/00353 , H03K5/145
摘要： A clock buffer circuit utilizing an LC circuit for jitter reduction. The circuit includes a differential amplifier that is coupled to a buffer stage. The output of the buffer circuit comprises the buffer stage output. An inductor and capacitor are coupled between the buffer stage output and ground. The values of the inductor and capacitor are specified such that the resonant frequency of the LC circuit corresponds to the nominal clock frequency. The entire buffer circuit including the capacitor and inductor may be fabricated on an integrated circuit. Alternatively the capacitor and/or inductor may comprise discrete components that are coupled to the buffer stage output. Additionally, multiple capacitors and/or inductors may be fabricated on the integrated circuit to permit the resonant frequency of the LC circuit to be adjusted to match the nominal clock frequency. The capacitor(s) and/or inductor(s) on the integrated circuit may be connected to integrated circuit contacts and coupled to the buffer stage output via external connections or alternatively, via semiconductor switches.
摘要翻译：使用LC电路的抖动降低的时钟缓冲电路。电路包括耦合到缓冲器级的差分放大器。缓冲电路的输出包括缓冲器级输出。电感和电容耦合在缓冲级输出和地之间。规定电感器和电容器的值，使得LC电路的谐振频率对应于标称时钟频率。包括电容器和电感器的整个缓冲电路可以在集成电路上制造。或者，电容器和/或电感器可以包括耦合到缓冲器级输出的分立元件。此外，可以在集成电路上制造多个电容器和/或电感器，以允许调整LC电路的谐振频率以匹配标称时钟频率。集成电路上的电容器和/或电感器可以连接到集成电路触点，并通过外部连接或通过半导体开关耦合到缓冲器级输出端。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式