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71. 发明申请

US20130126970A1 CONFIGURATION AND FABRICATION OF SEMICONDUCTOR STRUCTURE USING EMPTY AND FILLED WELLS 有权
标题翻译：使用空气和填充的孔的半导体结构的配置和制造
公开(公告)号：US20130126970A1
公开(公告)日：2013-05-23
申请号：US13670330
申请日：2012-11-06
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Constantin Bulucea , Sandeep Bahl , William French , Jeng-Jiun Yang , Donald Archer , David Courtney Parker , Prasad Chaparala
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/26513 , H01L21/2652 , H01L21/2658 , H01L21/26586 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.
摘要翻译：作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（“IGFET”）不同地使用的空阱区域和填充阱区域的组合，以实现所需的电子特性。相当少量的半导体阱掺杂剂靠近空穴的顶部。相当数量的半导体阱掺杂剂靠近填充井的顶部。一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

72. 发明申请

US20130121499A1 Frequency Domain Signal Processor For Close Talking Differential Microphone Array 审中-公开
标题翻译：频域信号处理器用于紧密通话的差分麦克风阵列
公开(公告)号：US20130121499A1
公开(公告)日：2013-05-16
申请号：US13734114
申请日：2013-01-04
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Yunhong Li , Lin Sun , Wei Ma
IPC分类号： G10K11/178
CPC分类号： G10K11/178 , H04M1/6008
摘要： A system and method for processing close talking differential microphone array (CTDMA) signals in which incoming microphone signals are transformed from time domain signals to frequency domain signals having separable magnitude and phase information. Processing of the frequency domain signals is performed using the magnitude information, following which phase information is reintroduced using phase information of one of the original frequency domain signals. As a result, high pass filtering effects of conventional differential signal processing of CTDMA signals are substantially avoided.
摘要翻译：用于处理紧密通话的差分麦克风阵列（CTDMA）信号的系统和方法，其中输入的麦克风信号从时域信号变换到具有可分离的幅度和相位信息的频域信号。使用幅度信息来执行频域信号的处理，随后使用原始频域信号之一的相位信息重新引入相位信息。结果，实质上避免了CTDMA信号的常规差分信号处理的高通滤波效应。

73. 发明申请

US20040268283A1 Method for creating, modifying, and simulating electrical circuits over the internet 有权
标题翻译：通过互联网创建，修改和模拟电路的方法
公开(公告)号：US20040268283A1
公开(公告)日：2004-12-30
申请号：US10603493
申请日：2003-06-24
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Jeffrey Robert Perry , Martin Garrison , Khang Nguyen , Richard Levin , Wanda Carol Garrett , Phillip Gibson , Benjamin H. Lee
IPC分类号： G06F009/455 , G06F017/50 , G06F017/60
CPC分类号： G06F17/5045 , G06F2217/04 , G06Q10/0875 , H05K3/0005 , H05K3/225
摘要： The present invention enables a user to create, modify, simulate and save an electrical circuit using an Internet browser over an Internet connection. The user can change the connectivity of the circuit as well as add and/or remove components in a free form manner. The schematic is displayed within a web page on the user's machine with which the user may interact. Block symbols may be used to represent at least a portion of the schematic.
摘要翻译：本发明使得用户能够通过因特网连接使用因特网浏览器创建，修改，模拟和保存电路。用户可以更改电路的连接性，并以自由形式添加和/或删除组件。原理图显示在用户可以与之交互的用户机器上的网页中。块符号可用于表示原理图的至少一部分。

74. 发明申请

US20040250839A1 Dual outlet nozzle for the combined edge bead removal and backside wash of spin coated wafers 有权
标题翻译：用于组合边缘珠去除和旋转涂层晶片背面清洗的双出口喷嘴
公开(公告)号：US20040250839A1
公开(公告)日：2004-12-16
申请号：US10461068
申请日：2003-06-12
申请人： National Semiconductor Corporation
发明人： Gary Robertson , Robert Boyd Finlay
IPC分类号： B08B007/00
CPC分类号： H01L21/6708 , B08B3/02 , G03F7/162 , G03F7/168 , H01L21/67051 , Y10S134/902
摘要： An apparatus and method for the improved combined edge bead removal and backside wash of spin coated semiconductor wafers is disclosed. This is preferably accomplished by providing a nozzle having a plurality of outlets adapted for the ejection of a cleaning fluid onto the backside of a semiconductor wafer. This cleaning fluid can be EEP or a similar EBR type of solvent. This dual outlet nozzle can be mounted to a stationary EBR arm, and preferably comprises two outlets located on a beveled top surface that are separated at a predetermined angle. The angle of this beveled top surface with respect to a horizontal plane of the processed wafer is preferably about 45 degrees, while the angle of each nozzle outlet with respect to a primary axis of the stationary EBR arm is also preferably about 45 degrees. Other angles are also possible in order to maximize solvent jet efficiency.
摘要翻译：公开了一种用于改进旋涂半导体晶片的组合边缘珠去除和背面清洗的装置和方法。这优选通过提供具有多个出口的喷嘴来实现，所述喷嘴适于将清洗流体喷射到半导体晶片的背面上。该清洗液可以是EEP或类似的EBR型溶剂。该双出口喷嘴可以安装到固定的EBR臂上，并且优选地包括位于以预定角度分离的倾斜顶表面上的两个出口。相对于经处理的晶片的水平面，该倾斜的顶表面的角度优选为约45度，而每个喷嘴出口相对于固定EBR臂的主轴线的角度也优选为约45度。为了使溶剂喷射效率最大化，其他角度也是可能的。

75. 发明申请

US20030209772A1 Electrical die contact structure and fabrication method 有权
标题翻译：电模接触结构及制造方法
公开(公告)号：US20030209772A1
公开(公告)日：2003-11-13
申请号：US10310724
申请日：2002-12-04
申请人： National Semiconductor Corporation
发明人： Ashok Prabhu
IPC分类号： H01L031/0216
CPC分类号： H01L27/14618 , H01L23/482 , H01L23/4827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The surface portion of the top protective layer includes electrical contact pads that are electrically connected with electrical contact pad extensions and with the integrated circuit. The second surface of the semiconductor substrate includes a multiplicity of backside electrical connectors that are in overlapping electrical contact with corresponding electrical contact pad extensions forming lap joint electrical connections between the backside electrical connectors and the corresponding electrical contact pad extensions. Methods for constructing such devices and connections are also disclosed.
摘要翻译：本发明的半导体器件包括形成在具有第一和第二表面和边缘的半导体衬底上的集成电路。第一表面包括与集成电路电连接的电接触垫。半导体衬底的第一表面包括具有延伸超过半导体衬底的边缘的表面部分的顶部保护层。顶部保护层的表面部分包括与电接触焊盘延伸部和集成电路电连接的电接触焊盘。半导体衬底的第二表面包括多个背面电连接器，其与相应的电接触焊盘延伸部重叠电接触，形成背面电连接器与相应的电接触焊盘延伸部之间的搭接部电连接。还公开了用于构造这种装置和连接的方法。

76. 发明申请

US20030134453A1 PROCESS AND STRUCTURE IMPROVEMENTS TO SHELLCASE STYLE PACKAGING TECHNOLOGY 有权
标题翻译：过程和结构改进对鞋底包装技术的影响
公开(公告)号：US20030134453A1
公开(公告)日：2003-07-17
申请号：US10044805
申请日：2002-01-11
申请人： National Semiconductor Corporation
发明人： Ashok Prabhu , Nikhil Kelkar , Anindya Poddar
IPC分类号： H01L021/44 , H01L021/48 , H01L021/50 , H01L023/02
CPC分类号： H01L23/3135 , H01L23/3114 , H01L23/49805 , H01L2924/0002 , H01L2924/00
摘要： A variety of improved shell case style packages as well as shell case style wafer level packaging processes are described. Generally, in shell case style packaging, traces are patterned on the top surface of a wafer. In some embodiments, the conductors formed along the sides of the package are formed from at least a couple conductor layers to improve the adhesion of the conductors to the traces formed on the top surface of the devices. In some embodiments the conductors are patterned during processing such that the conductors are not cut during the wafer dicing operation. This arrangement is particularly useful when the conductors are formed at least partially from aluminum (or other metals that oxidize in ambient air). In other embodiments, BCB is not used under the trace layer in regions that will have notches formed therein so that the resulting package does not have any exposed BCB/trace junctions. In some embodiments, no BCB layer whatsoever is applied during packaging. In other embodiments, BCB is used, but the BCB layer is patterned to avoid dice line areas that will later be trenched or notched.
摘要翻译：描述了各种改进的壳壳式包装以及壳壳式晶片级封装工艺。通常，在外壳外壳型封装中，迹线图案化在晶片的顶表面上。在一些实施例中，沿着封装的侧面形成的导体由至少一对导体层形成，以改善导体与形成在器件的顶表面上的迹线的粘附。在一些实施例中，在处理过程中导体被图案化，使得导体在晶片切割操作期间不被切割。当导体至少部分地由铝（或在环境空气中氧化的其它金属）形成时，这种布置是特别有用的。在其它实施例中，BCB不在其中形成有缺口的区域中的迹线层下使用，使得所得到的封装不具有任何暴露的BCB /迹线结。在一些实施例中，在包装期间不施加任何BCB层。在其他实施例中，使用BCB，但是BCB层被图案化以避免稍后将被沟槽或切口的骰子线区域。

77. 发明申请

US20030026081A1 Ceramic optical sub-assembly for optoelectronic modules 有权
标题翻译：陶瓷光电子组件用于光电模块
公开(公告)号：US20030026081A1
公开(公告)日：2003-02-06
申请号：US10165711
申请日：2002-06-06
申请人： National Semiconductor Corporation
发明人： Jia Liu , Luu Thanh Nguyen , Ken Pham , William Paul Mazotti , Bruce Carlton Roberts , Stephen Andrew Gee , John P. Briant
IPC分类号： H05K007/02
CPC分类号： H05K1/0219 , G02B6/4201 , H05K1/189 , H05K3/403 , H05K2201/0715 , H05K2201/09236 , H05K2201/10121
摘要： Optoelectronic components, specifically, ceramic optical sub-assemblies are described. In one aspect, the optoelectronic component includes a ceramic base substrate having a pair of angled (or substantially perpendicular) faces. The electrical traces are formed directly on the ceramic surfaces and extend between the pair of faces. A semiconductor chip assembly is mounted on the first face of the ceramic base substrate and a photonic device is mounted on the second face. Both the semiconductor chip assembly and the photonic device are electrically connected to traces on the ceramic base substrate. The semiconductor chip assembly is generally arranged to be electrically connected to external devices. The photonic devices are generally arranged to optically communicate with one or more optical fibers. The described structure may be used with a wide variety of photonic devices. It is particularly well adapted for use with vertical cavity surface emitting lasers (or laser arrays) and detectors (or detector arrays). In some embodiments, at least the cathode of the photonic device is soldered directly to a cathode pad on the base substrate. Similarly, in some embodiments, the semiconductor chip assembly is electrically connected to the base substrate by direct soldering. Specific base substrate structures are disclosed as well.
摘要翻译：光电子部件，特别是陶瓷光学子组件被描述。在一个方面，光电子部件包括具有一对成角度（或大致垂直）面的陶瓷基底基板。电迹线直接形成在陶瓷表面上并在一对面之间延伸。半导体芯片组件安装在陶瓷基底基板的第一面上，光子器件安装在第二面上。半导体芯片组件和光子器件都与陶瓷基底衬底上的迹线电连接。半导体芯片组件通常被布置成电连接到外部设备。光子器件通常布置成与一根或多根光纤光学通信。所描述的结构可以与各种各样的光子器件一起使用。它特别适用于垂直腔表面发射激光（或激光阵列）和检测器（或检测器阵列）。在一些实施例中，光子器件的至少阴极直接焊接到基底衬底上的阴极焊盘。类似地，在一些实施例中，半导体芯片组件通过直接焊接电连接到基底基板。还公开了特定的基底结构。

78. 发明申请

US20020181181A1 Fuse protected shunt regulator having improved control characteristics 有权
标题翻译：具有改进的控制特性的保险丝保护的并联调节器
公开(公告)号：US20020181181A1
公开(公告)日：2002-12-05
申请号：US10201765
申请日：2002-07-22
申请人： National Semiconductor Corporation
发明人： Gregory J. Smith
IPC分类号： H02H005/04
CPC分类号： G05F1/613
摘要： A shunt regulator circuit and method for protecting the circuit having a plurality of fuses parallely arranged in a bank so that lower rated fuse can be used while improving the control characteristics of activating the fuse elements. The circuit operates in one of two modes, a shunt regulator mode and a fuse activation mode. In the shunt regulator mode, a feedback circuit prevents any fuse that has blown open form loading a feedback signal to the regulator amplifier of the circuit. In fuse activation mode, each fuse is selectively activated so that a large amount of current is caused to flow through the fuse element until it blows open. This continues for each fuse element in the bank until the safety concern has been eliminated.
摘要翻译：一种用于保护具有并联布置在一个组中的多个保险丝的电路的并联调节器电路和方法，使得可以使用较低额定的保险丝，同时改善激活熔丝元件的控制特性。电路工作在两种模式之一，分流调节器模式和保险丝激活模式。在分流调节器模式下，反馈电路可以防止任何已断开的保险丝将反馈信号加载到电路的稳压器放大器。在保险丝激活模式下，每个保险丝被选择性地激活，使得大量电流流过保险丝元件直到其打开。对于银行中的每个保险丝元件，这将继续进行，直到安全考虑被消除为止。

79. 发明申请

US20020135421A1 Differential current mirror system and method 有权
标题翻译：差分电流镜系统及方法
公开(公告)号：US20020135421A1
公开(公告)日：2002-09-26
申请号：US10122770
申请日：2002-04-11
申请人： National Semiconductor Corporation
发明人： Abhijit M. Phanse , Michael X. Maida
IPC分类号： H03F003/45
CPC分类号： H03F3/45183 , H03F2203/45344 , H03F2203/45544
摘要： There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.
摘要翻译：公开了一种差分电流镜系统和方法，用于提供差分输出电流信号，其中差分输入电流信号与共模电流信号被拒绝。该系统包括一对二极管连接的晶体管和差分放大器。一对二极管连接的晶体管包括耦合在一起的第一和第二晶体管。差分放大器包括以差分放大器配置耦合在一起的第三和第四晶体管。第三晶体管的栅极接收来自第一晶体管的漏极的第一输入电流信号，第四晶体管的栅极从第二晶体管的漏极接收第二输入电流信号。

80. 发明申请

US20020079540A1 Diode junction based electrostatic discharge (ESD) protection structure 审中-公开
标题翻译：二极管结基静电放电（ESD）保护结构
公开(公告)号：US20020079540A1
公开(公告)日：2002-06-27
申请号：US09747848
申请日：2000-12-21
申请人： National Semiconductor Corporation
发明人： Vladislav Vashchenko , Alexei Sadovnikov
IPC分类号： H01L023/62
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection structure for use in high speed (e.g., 5-7 GHz RF frequency) CMOS and BiCMOS ICs that has a low leakage current and a low equivalent capacitance. The ESD protection structure can be manufactured using conventional processes and includes a semiconductor substrate of a first conductivity type (e.g., a Pnull epitaxial silicon semiconductor substrate) with a well region of a second conductivity type (e.g., an Nnull well region) disposed therein. The structure also includes a first region of the first conductivity type (e.g., a Pnull first region) disposed in the well region on the semiconductor substrate, as well as a second region of the second conductivity type (e.g., an Nnull second region) disposed in and on the semiconductor substrate and spaced apart from the first region. Furthermore, an electrical isolation region is disposed in the semiconductor substrate between the first region and the second region. The ESD protection structure exhibits diode-like electrical behavior with the first region serving as an anode and the second region serving as a cathode, including a low equivalent capacitance and low reverse bias leakage current.
摘要翻译：用于具有低漏电流和低等效电容的高速（例如5-7GHz RF频率）CMOS和BiCMOS IC的ESD保护结构。 ESD保护结构可以使用常规方法制造，并且包括具有第二导电类型的阱区（例如，N-阱区）的第一导电类型的半导体衬底（例如，P-外延硅半导体衬底）其中。该结构还包括设置在半导体衬底上的阱区中的第一导电类型的第一区域（例如，P +第一区域），以及设置在第二导电类型（例如，N +第二区域）的第二区域在半导体衬底中和之上并且与第一区域间隔开。此外，在第一区域和第二区域之间的半导体衬底中设置电隔离区域。 ESD保护结构表现出二极管状的电性能，第一区域用作阳极，第二区域用作阴极，包括低等效电容和低反向偏置漏电流。

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