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71. 发明申请

US20050110039A1 Modification of carrier mobility in a semiconductor device 有权
公开(公告)号：US20050110039A1
公开(公告)日：2005-05-26
申请号：US10718920
申请日：2003-11-21
申请人： Min-Hwa Chi , Wai-Yi Lien
发明人： Min-Hwa Chi , Wai-Yi Lien
IPC分类号： H01L21/46 , H01L21/76 , H01L27/20 , H01L29/06 , H01L29/73 , H01L29/78
CPC分类号： H01L29/7846 , H01L29/0696 , H01L29/78
摘要： Tensile or compressive stress may be added in one or more selected locations to the biaxial residual stress existing in the channel of a semiconductor device, such as a MOSFET. The periphery of the active area containing the channel is modified by following layout procedures that result in forming outward protrusions of or inward depressions in the periphery of the active area and its surrounding shallow trench isolation during generally otherwise conventional fabrication of the device.

72. 发明申请

US20050026406A1 Method for fabricating poly patterns 失效
标题翻译：多模式制作方法
公开(公告)号：US20050026406A1
公开(公告)日：2005-02-03
申请号：US10631251
申请日：2003-07-31
申请人： Ching-Chen Hao , Hung-Jen Lin , Min-Hwa Chi , Chih-Heng Shen
发明人： Ching-Chen Hao , Hung-Jen Lin , Min-Hwa Chi , Chih-Heng Shen
IPC分类号： H01L21/027 , H01L21/28 , H01L21/283 , H01L21/31 , H01L21/3213 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/28211 , H01L21/28035 , H01L21/28176 , H01L21/28194 , H01L21/32139 , H01L21/823828
摘要： A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form the polysilicon patterns and an oxidizing step is performed. The mask layer is removed after the oxidizing step is performed.
摘要翻译：一种制造多晶硅图案的方法。该方法包括在衬底上沉积多晶硅。根据应用，多晶硅可以被掺杂或预掺杂。应用掩模层并构图。此后，蚀刻多晶硅以形成多晶硅图案，并进行氧化步骤。在进行氧化步骤之后，去除掩模层。

73. 发明授权

US06670279B1 Method of forming shallow trench isolation with rounded corners and divot-free by using in-situ formed spacers 有权
标题翻译：通过使用原位形成的间隔物形成具有圆角的浅沟槽隔离和无凹槽的方法
公开(公告)号：US06670279B1
公开(公告)日：2003-12-30
申请号：US10068055
申请日：2002-02-05
申请人： Chih-Yang Pai , Bi-Ling Chen , Min-Hwa Chi
发明人： Chih-Yang Pai , Bi-Ling Chen , Min-Hwa Chi
IPC分类号： H01L2100
CPC分类号： H01L21/76235
摘要： A method of fabricating an STI structure comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. A hard mask layer is formed over the pad oxide layer. The hard mask layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure. The opening having exposed side walls. A spacer layer is formed over the patterned hard mask layer, the exposed side walls of the opening and lining the opening. The structure is subjected to an STI trench etching process to: (1) remove the spacer layer from over the patterned hard mask layer; form spacers over the side walls; (2) the spacers being formed in-situ from the spacer layer; and (3) etch an STI trench within the silicon structure wherein the spacers serve as masks during at least a portion of time in which the STI trench is formed. The STI trench having corners. Any remaining portion of the spacers are removed. A liner oxide is formed at least within the STI trench whereby the liner oxide has rounded corners proximate the STI trench corners. An STI fill layer is formed over the patterned hard mask layer and filling the liner oxide lined STI trench. The STI fill layer is planarized, stopping on the patterned hard mask layer. The patterned hard mask layer and the patterned pad oxide layer are removed to form a divot-free STI structure having rounded corners.
摘要翻译：一种制造STI结构的方法，包括以下步骤。提供了具有形成在其上的衬垫氧化物层的硅结构。在衬垫氧化物层上形成硬掩模层。将硬掩模层和焊盘氧化物层图案化以形成露出硅结构的一部分的开口。开口具有暴露的侧壁。在图案化的硬掩模层，开口的暴露的侧壁和衬里的开口上形成间隔层。对该结构进行STI沟槽蚀刻处理，以：（1）从图案化的硬掩模层上方去除间隔层; 在侧壁上形成间隔物; （2）间隔物从间隔层原位形成; 和（3）蚀刻硅结构内的STI沟槽，其中在形成STI沟槽的至少一部分时间中，间隔物用作掩模。 STI沟槽有角。去除间隔物的任何剩余部分。至少在STI沟槽内形成衬垫氧化物，由此衬垫氧化物在STI沟槽角附近具有圆角。在图案化的硬掩模层上形成STI填充层，并填充衬里氧化物衬里的STI沟槽。 STI填充层被平坦化，停止在图案化的硬掩模层上。图案化的硬掩模层和图案化的衬垫氧化物层被去除以形成具有圆角的无纹隙的STI结构。

74. 发明授权

US06262447B1 Single polysilicon DRAM cell and array with current gain 有权
标题翻译：单个多晶硅DRAM单元和阵列具有电流增益
公开(公告)号：US06262447B1
公开(公告)日：2001-07-17
申请号：US09422051
申请日：1999-10-20
申请人： Min-hwa Chi
发明人： Min-hwa Chi
IPC分类号： H01L27108
CPC分类号： H01L27/108
摘要： A two-dimensional array of single polysilicon DRAM cells is disclosed. The array comprises a plurality of DRAM cells arranged in a two-dimensional matrix, wherein each of the DRAM cells comprises: a deep n-well in a silicon substrate; a p-well within the deep n-well; a gate structure over and straddling the deep n-well and the p-well; and a n+ region within the p-well and adjacent to a sidewall of the gate structure. The array is connected together by a plurality of column bitlines, each of the column bitlines connected to the n+ regions of all of the DRAM cells that are in a common column. Further, a plurality of row wordlines are provided, each of the row wordlines connected to the gate structures of all of the DRAM cells that are in a common row.
摘要翻译：公开了单个多晶硅DRAM单元的二维阵列。阵列包括以二维矩阵排列的多个DRAM单元，其中每个DRAM单元包括：硅衬底中的深n阱; 深井内的p井; 一个门结构，跨越深n井和p井; 以及p阱内的n +区域，并且与栅极结构的侧壁相邻。阵列通过多个列位线连接在一起，每个列位线连接到位于公共列中的所有DRAM单元的n +区。此外，提供多个行字线，每个行字线连接到处于公共行的所有DRAM单元的栅极结构。

75. 发明授权

US06200852B1 Method to fabricate DRAM capacitor 有权
标题翻译：制造DRAM电容的方法
公开(公告)号：US06200852B1
公开(公告)日：2001-03-13
申请号：US09393705
申请日：1999-09-10
申请人： Chine-Gie Lou , Min-Hwa Chi
发明人： Chine-Gie Lou , Min-Hwa Chi
IPC分类号： H01L218242
CPC分类号： H01L21/3185 , H01L27/1085 , H01L28/56
摘要： A method for fabricating DRAM capacitor dielectric layer with high permittivity is disclosed. In the first preferred embodiment, the process temperature is about 700° C. or below. Thus this embodiment is apt to utilize for DRAM with metal silicide transistor. In the processes, the multiple thin silicon nitride layers are formed on respective film surface to obtain pinhole defects unmatched dielectric layer. The second preferred embodiment, the processes uses different CVD method to deposit multiple thin silicon nitride layers and thus pinhole defects are unmatched. Both of two embodiments provide capacitor dielectric layer with least leakage current so as to increase the capacitance.
摘要翻译：公开了一种用于制造具有高介电常数的DRAM电容器介电层的方法。在第一优选实施例中，工艺温度为约700℃或更低。因此，本实施例适用于具有金属硅化物晶体管的DRAM。在这些工艺中，在各个薄膜表面上形成多个薄的氮化硅层，以获得不匹配的电介质层的针孔缺陷。在第二优选实施方案中，该方法使用不同的CVD方法沉积多个薄的氮化硅层，因此针孔缺陷是不匹配的。两个实施例都提供具有最小漏电流的电容器电介质层，以增加电容。

76. 发明授权

US06181601B2 Flash memory cell using p+/N-well diode with double poly floating gate 有权
标题翻译：使用具有双多晶浮栅的p + / N阱二极管的闪存单元
公开(公告)号：US06181601B2
公开(公告)日：2001-01-30
申请号：US09454490
申请日：1999-12-02
申请人： Min-hwa Chi
发明人： Min-hwa Chi
IPC分类号： G11C1134
CPC分类号： G11C16/0416 , H01L29/8616
摘要： A flash memory cell formed in a semiconductor substrate is disclosed. The cell includes an n-well formed within the substrate. Next, a p+ drain region is formed within the n-well. A floating gate is formed above the n-well being separated from the substrate by a thin oxide layer. The floating gate is formed adjacent to the p+ drain region. Finally, a control gate is formed above the floating gate, the floating gate and the control gate being separated by a dielectric layer. The new cell is read by measuring the GIDL current at p+/n-well junction, which is exponentially modulated by the floating gate potential (or its net charge). The new cell is programmed by band-to-band hot electron injection and is erased by F-N tunneling through the overlap area of floating gate and n-well.
摘要翻译：公开了一种形成在半导体衬底中的闪存单元。电池包括在衬底内形成的n阱。接下来，在n阱内形成p +漏极区域。在n阱之上形成浮栅，其通过薄氧化层与衬底分离。浮置栅极与p +漏极区域相邻地形成。最后，在浮置栅极上形成控制栅极，浮置栅极和控制栅极被介电层分开。通过测量p + / n-well结的GIDL电流来读取新单元，该电流由浮置栅极电位（或其净电荷）指数式调制。新电池通过带 - 带热电子注入进行编程，并通过F-N穿透浮栅和n阱的重叠区擦除。

77. 发明授权

US6133604A NOR array architecture and operation methods for ETOX cells capable of full EEPROM functions 有权
标题翻译：具有完整EEPROM功能的ETOX单元的NOR阵列结构和操作方法
公开(公告)号：US6133604A
公开(公告)日：2000-10-17
申请号：US295017
申请日：1999-04-20
申请人： Min-hwa Chi
发明人： Min-hwa Chi
IPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , H01L27/115 , H01L29/788 , H01L29/00
CPC分类号： G11C16/16 , G11C16/0416 , G11C16/10 , H01L29/7885 , H01L27/115
摘要： A NOR array architecture allowing single bit, row, and column programming and erase operations is disclosed. The NOR array architecture comprises: a plurality of ETOX cells formed in a deep n-well, each of the ETOX cell having: (1) a control gate; (2) a floating gate insulated from and formed substantially underneath the control gate; (3) a p-well formed in the n-well and underneath the floating gate and the control gate; (4) a drain implant formed in the p-well adjacent to the floating gate; and (5) a source implant formed in the p-well adjacent to the floating gate. The ETOX cells are formed into a two-dimensional array including a plurality of rows and a plurality of columns. Each of the control gates of the ETOX cells in adjacent two rows sharing a common row are connected to a row wordline. Each of the source implants of the ETOX cells sharing a common row are connected to a row sourceline. Each of the drain implants of the ETOX cells sharing a common column are connected to a column bitline. Finally, each of the p-wells of the ETOX cells in a common column are connected together to a common p-well bias line.
摘要翻译：公开了允许单个位，行和列编程和擦除操作的NOR阵列架构。 NOR阵列架构包括：形成在深n阱中的多个ETOX单元，每个ETOX单元具有：（1）控制栅极; （2）基本上位于控制栅极下方的绝缘并形成的浮栅; （3）在n阱中并在浮动栅极和控制栅极下形成的p阱; （4）形成在与浮动栅极相邻的p阱中的漏极注入; 和（5）形成在与浮置栅极相邻的p阱中的源极注入。 ETOX单元形成为包括多行和多列的二维阵列。共享公共行的相邻两行中的ETOX单元的每个控制栅极连接到行字线。共享公共行的ETOX单元的每个源植入物都连接到行源行。共享公共列的ETOX单元的每个漏极注入连接到列位线。最后，共同柱中的ETOX单元的每个p阱连接在一起，形成一个普通的p阱偏置线。

78. 发明授权

US6060742A ETOX cell having bipolar electron injection for substrate-hot-electron program 有权
标题翻译：具有用于基板热电子程序的双极电子注入的ETOX单元
公开(公告)号：US6060742A
公开(公告)日：2000-05-09
申请号：US334080
申请日：1999-06-16
申请人： Min-hwa Chi , Min-Chie Jung
发明人： Min-hwa Chi , Min-Chie Jung
IPC分类号： H01L29/788 , H01L29/76 , G11C14/00
CPC分类号： H01L29/7885
摘要： An ETOX cell that has improved injection of electrons from a forward biased deep n-well to p-well junction underneath the channel area of a triple-well ETOX cell during substrate hot electron (SHE) programming. The ETOX cell has a control gate, a floating gate, a deep n-well formed in the substrate, a buried n+ layer in the deep n-well, a p-well formed in the n-well and atop the buried n+ layer, a drain implant formed in the p-well, and a source implant formed in the p-well. The buried n+ layer enhances the parasitic bipolar action between the n+ source/drain (as collector), the p-well (as base), and the buried n+ layer (as emitter). The parasitic transistor amplifies the amount of seed electrons injected into the p-well, which in turn results in significantly faster programming of the ETOX cell.
摘要翻译：在衬底热电子（SHE）编程期间，ETOX电池已经从三阱ETOX电池的通道区域的正向偏置的深n阱到p阱结点改进了电子注入。 ETOX单元具有控制栅极，浮置栅极，在衬底中形成的深n阱，深n阱中的掩埋n +层，在n阱中形成的p阱以及掩埋的n +层顶部，形成在p阱中的漏极注入，以及形成在p阱中的源极注入。掩埋的n +层增强了n +源极/漏极（作为集电极），p阱（作为基极）和掩埋的n +层（作为发射极）之间的寄生双极性作用。寄生晶体管放大注入到p阱中的种子电子的量，这又导致ETOX细胞的编程显着更快。

79. 发明授权

US06018177A DRAM cell and array to store two-bit data 有权
标题翻译： DRAM单元和阵列存储两位数据
公开(公告)号：US06018177A
公开(公告)日：2000-01-25
申请号：US257836
申请日：1999-02-25
申请人： Min-Hwa Chi
发明人： Min-Hwa Chi
IPC分类号： G11C11/56 , H01L27/108
CPC分类号： G11C11/565 , H01L27/108
摘要： A DRAM cell capable of storing two bits of digital data as four levels of stored charge within the DRAM cell is disclosed. The four level DRAM cell has a pass transistor, a trench capacitor, and a stack capacitor. The pass transistors has a source connected to a bit line voltage generator to control placement of the charge within the four level DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain and a bottom plate connected to a substrate biasing voltage source. The stack capacitor has a first plate connected to the drain and a second plate connected to a coupling-gate voltage generator. The coupling-gate voltage generator will provide four levels of voltage that will indicate the level of charge to be stored within the four level DRAM cell. An interconnecting block that will interconnect the top plate of the trench capacitor to the first plate of the stack capacitor. The interconnection point between the trench capacitor and the stack capacitor will form the storage node that will retain the level of charge that indicates the state of the two bits of digital data. Four level DRAM cells will be arranged in a plurality of rows and columns to form an array of four level DRAM cells.
摘要翻译：公开了能够将两比特数字数据存储在DRAM单元内的四级存储电荷的DRAM单元。四级DRAM单元具有传输晶体管，沟槽电容器和堆叠电容器。传输晶体管具有连接到位线电压发生器的源，以控制四电平DRAM单元内的电荷的放置，连接到字线电压发生器的栅极以控制DRAM单元的激活和漏极。沟槽电容器具有连接到漏极的顶板和连接到衬底偏置电压源的底板。堆叠电容器具有连接到漏极的第一板和连接到耦合栅极电压发生器的第二板。耦合栅极电压发生器将提供四个电平，其将指示要存储在四电平DRAM单元内的电荷电平。互连块，其将沟槽电容器的顶板与堆叠电容器的第一板互连。沟槽电容器和堆叠电容器之间的互连点将形成存储节点，其将保持指示两位数字数据的状态的电荷电平。四级DRAM单元将被布置成多行和列以形成四级DRAM单元的阵列。

80. 发明授权

US6008508A ESD Input protection using a floating gate neuron MOSFET as a tunable trigger element 失效
标题翻译： ESD输入保护使用浮动栅极神经元MOSFET作为可调触发元件
公开(公告)号：US6008508A
公开(公告)日：1999-12-28
申请号：US713026
申请日：1996-09-12
申请人： Albert Bergemont , Min-hwa Chi
发明人： Albert Bergemont , Min-hwa Chi
IPC分类号： H01L27/02 , H01L29/06
CPC分类号： H01L27/0262 , H01L2924/0002
摘要： Disclosed is a floating gate neuron MOS transistor that may be incorporated into devices such as low voltage silicon control rectifiers for protection of internal circuits against electrostatic discharge. The transistor includes two or more input gates capacitively coupled to the floating gate. By adjusting the coupling ratio of the input gates, it is possible to control the transistor drain turn-on voltage very precisely and thereby turn on the rectifier without relying on avalanche breakdown of the transistor.
摘要翻译：公开了一种浮栅神经元MOS晶体管，其可以并入诸如用于保护内部电路免受静电放电的低压硅控制整流器的器件中。晶体管包括电容耦合到浮置栅极的两个或更多个输入栅极。通过调整输入栅极的耦合比，可以非常精确地控制晶体管漏极导通电压，从而导通整流器，而不依赖于晶体管的雪崩击穿。

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