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71. 发明授权

US06825086B2 Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner 失效
标题翻译：应变硅沟道CMOS与牺牲浅沟槽隔离氧化物衬垫
公开(公告)号：US06825086B2
公开(公告)日：2004-11-30
申请号：US10345728
申请日：2003-01-17
申请人： Jong-Jan Lee , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21336
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807
摘要： A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.
摘要翻译：已经提供了应变硅（Si）沟道CMOS器件浅沟槽隔离（STI）氧化物区域及其形成方法。该方法包括：形成Si衬底; 形成覆盖在Si衬底上的弛豫SiGe层或者具有掩埋氧化物（BOX）层的绝缘体上硅锗（SGOI）衬底; 形成覆盖弛豫SiGe层的应变Si层; 形成覆盖在应变Si层上的氧化硅层; 形成覆盖所述氧化硅层的氮化硅层; 蚀刻氮化硅层，氧化硅层，应变Si层和弛豫SiGe层，形成具有沟槽角和沟槽表面的STI沟槽; 在STI沟槽表面上形成牺牲氧化物衬垫; 响应于形成牺牲氧化物衬垫，在STI沟槽角处减少应力; 去除牺牲氧化物衬垫; 并用氧化硅填充STI沟槽。

72. 发明授权

US06699764B1 Method for amorphization re-crystallization of Si1-xGex films on silicon substrates 失效
标题翻译：硅衬底上Si1-xGex薄膜的非晶化再结晶方法
公开(公告)号：US06699764B1
公开(公告)日：2004-03-02
申请号：US10238146
申请日：2002-09-09
申请人： Douglas J. Tweet , Jer-shen Maa , Jong-Jan Lee , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jer-shen Maa , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21336
CPC分类号： H01L21/263 , C30B1/023 , C30B1/04 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02694 , H01L29/1054 , H01L29/165 , Y10S438/933
摘要： A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.
摘要翻译：在硅衬底上制造Si1-XGeX膜的方法包括制备硅衬底; 在硅衬底上外延沉积形成Si1-XGeX / Si界面的Si1-XGeX层; 在Si1-XGeX层上外延生长硅帽; 通过Si1-XGeX层将氢离子注入Si1-XGeX / Si界面以下约3nm至100nm之间的深度; 将Si1-XGeX层非晶化以形成无定形的梯度SiGe层; 并在约650℃至1100℃的温度下对该结构退火约十秒至六十分钟以使SiGe层重结晶。

73. 发明授权

US06242771B1 Chemical vapor deposition of PB5GE3O11 thin film for ferroelectric applications 失效
标题翻译：用于铁电应用的PB5GE3O11薄膜的化学气相沉积
公开(公告)号：US06242771B1
公开(公告)日：2001-06-05
申请号：US09291688
申请日：1999-04-13
申请人： Sheng Teng Hsu , Chien Hsiung Peng , Jong Jan Lee
发明人： Sheng Teng Hsu , Chien Hsiung Peng , Jong Jan Lee
IPC分类号： H01L29788
CPC分类号： H01L28/55 , C23C16/40 , H01L21/31604 , H01L21/31691 , H01L29/516 , H01L29/78391
摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; treating the device area to form area for a source, gate and drain region; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb5Ge3O11 FE layer by Chemical vapor deposition (CVD), and depositing an upper electrode; and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell includes: a single-crystal silicon substrate including an active region having source, gate and drain regions therein; a FEM gate unit including a lower electrode, a c-axis oriented Pb5Ge3O11 FE layer formed by CVD and an upper electrode; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source, gate and drain electrode.
摘要翻译：在单晶硅的衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括：形成用于FEM门单元的硅器件区域; 处理器件区域以形成源极，栅极和漏极区域; 在所述栅极结区域上沉积FEM栅极单元，包括沉积下电极，通过化学气相沉积（CVD）沉积c轴取向的Pb5Ge3O11FE层，以及沉积上电极; 以及围绕所述FEM门单元沉积绝缘结构。铁电存储器（FEM）单元包括：单晶硅衬底，其包括其中具有源极，栅极和漏极区域的有源区; 包括下电极，由CVD形成的c轴取向Pb5Ge3O11FE层和上电极的有限元门单元; 绝缘层，具有覆盖接合区域的上表面，FEM门单元和衬底; 以及源极，栅极和漏极。

74. 发明授权

US6117691A Method of making a single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization 有权
标题翻译：制造具有不对称铁电极化的单晶体管铁电存储单元的方法
公开(公告)号：US6117691A
公开(公告)日：2000-09-12
申请号：US287726
申请日：1999-04-07
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： G11C11/22 , H01L21/28 , H01L21/8246 , H01L21/84 , H01L27/115 , H01L29/78 , H01G7/06
CPC分类号： H01L21/84 , G11C11/22 , H01L21/28291 , H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L29/78391 , G11C11/223
摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of the first type in the conductive channel well of the second type to form a conductive channel of the first conductivity type for use as a gate junction region, implanting doping impurities of the second type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of the second conductivity type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region.A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of the first conductive type formed in the second conductivity type well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, doped to form conductive channels of second conductive type. A FEM gate unit overlays the conductive channel of the gate junction region. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell.
摘要翻译：在硅衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括将第一类型的掺杂杂质注入到衬底中以形成第一类型的导电沟道，将第二类型的掺杂杂质注入到所述第一类型的导电通道形成第二类型的导电通道阱，在所述第二类型的导电通道阱中注入所述第一类型的掺杂杂质，以形成用作栅极结区域的第一导电类型的导电沟道在栅极结区域的任一侧将第二类型的导电沟道子阱中的第二类型的掺杂杂质注入，以形成用作源极结区域和漏极结区域的第二导电类型的多个导电沟道; 以及在栅极结区域上沉积FEM栅极单元。铁电存储单元包括第一导电类型的硅衬底，形成在衬底中的第二导电类型的阱结构，形成在第二导电类型阱结构中的第一导电类型的结构，用作栅极结区域。源极结区域和漏极结区域位于栅极结区域的任一侧的子阱中，被掺杂形成第二导电类型的导电沟道。有限元栅极单元覆盖栅极结区域的导电沟道。绝缘层覆盖了连接区域，FEM栅极单元和衬底。合适的电极连接到存储单元中的各种有源区。

75. 发明授权

US6048738A Method of making ferroelectric memory cell for VLSI RAM array 失效
标题翻译：制造VLSI RAM阵列的铁电存储单元的方法
公开(公告)号：US6048738A
公开(公告)日：2000-04-11
申请号：US870375
申请日：1997-06-06
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： G11C11/22 , H01L21/28 , H01L21/8246 , H01L21/84 , H01L27/115 , H01L29/78 , H01G7/06
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28291 , H01L21/84 , H01L27/11585 , H01L27/1159 , H01L29/78391 , G11C11/223
摘要： A method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate junction region, forming a MOS capacitor on the conductive channel of the first type, depositing an FEM capacitor over the MOS capacitor, thereby forming a stacked gate unit, implanting doping impurities of a second type in the silicon substrate on either side of the gate junction region to form a conductive channel of a second type for use as a source junction region and a drain junction region, and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell constructed according to the invention includes a silicon substrate, a gate region located in said substrate, a source junction region and a drain junction region located on either side of said gate region, a MOS capacitor, a FEM capacitor, wherein said FEM capacitor is stacked on and overlays at least a portion of said MOS capacitor, thereby forming, with said MOS capacitor, a stacked gate unit.
摘要翻译：在硅衬底上形成半导体存储器件的方法包括在硅衬底中注入第一类型的掺杂杂质以形成用作栅极结区域的第一类型的导电沟道，在导电沟道上形成MOS电容器第一类型，在MOS电容器上沉积FEM电容器，从而形成堆叠栅极单元，在栅极结区域的任一侧上在硅衬底中注入第二类型的掺杂杂质以形成第二类型的导电沟道用于作为源极结区域和漏极结区域，以及围绕FEM栅极单元沉积绝缘结构。根据本发明构造的铁电存储器（FEM）单元包括硅衬底，位于所述衬底中的栅极区，位于所述栅极区两侧的源极结区域和漏极结区域，MOS电容器，FEM电容器，其中所述FEM电容器堆叠在所述MOS电容器的至少一部分上并覆盖所述MOS电容器，从而与所述MOS电容器形成堆叠栅极单元。

76. 发明授权

US5891782A Method for fabricating an asymmetric channel doped MOS structure 失效
标题翻译：制造不对称沟道掺杂MOS结构的方法
公开(公告)号：US5891782A
公开(公告)日：1999-04-06
申请号：US918678
申请日：1997-08-21
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L21/8234
CPC分类号： H01L29/78624 , H01L29/66772 , H01L29/78696
摘要： A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger I.sub.d currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.
摘要翻译：提供了一种形成在沟道区和漏极之间没有轻掺杂漏极（LDD）区的MOS晶体管的方法。沟道区域是在淀积栅极氧化物层之后由倾斜的离子注入形成的。相对于栅电极的长度，倾斜注入形成相对短的沟道长度。通道的位置偏移，并直接与源相邻。在漏极附近的栅极下方的非沟道区域替代通道和漏极之间的LDD区域。这种漏极扩展用于更均匀地分布电场，使得可以实现大的击穿电压。较小的通道长度和消除与源极相邻的LDD区域起到降低源极和漏极之间的电阻的作用。以这种方式，获得更大的Id电流和更快的开关速度。还提供了具有短的偏置沟道和漏极延伸的MOS晶体管。

77. 发明授权

US09159502B2 Supercapacitor with hexacyanometallate cathode, activated carbon anode, and non-aqueous electrolyte 有权
标题翻译：具有六金属金属阴极，活性炭阳极和非水电解质的超级电容器
公开(公告)号：US09159502B2
公开(公告)日：2015-10-13
申请号：US13603322
申请日：2012-09-04
申请人： Yuhao Lu , Sean Andrew Vail , Hidayat Kisdarjono , Jong-Jan Lee
发明人： Yuhao Lu , Sean Andrew Vail , Hidayat Kisdarjono , Jong-Jan Lee
IPC分类号： H01M2/16 , H01G11/30
CPC分类号： H01G11/30 , Y02E60/13 , Y10T29/417
摘要： A supercapacitor is provided with a method for fabricating the supercapacitor. The method provides dried hexacyanometallate particles having a chemical formula AmM1xM2y(CN)6.pH2O with a Prussian Blue hexacyanometallate, crystal structure, where A is an alkali or alkaline-earth cation, and M1 and M2 are metals with 2+ or 3+ valance positions. The variable m is in the range of 0.5 to 2, x is in the range of 0.5 to 1.5, y is in the range of 0.5 to 1.5, and p is in the range of 0 to 6. The hexacyanometallate particles are mixed with a binder and electronic conductor powder, to form a cathode comprising AmM1xM2y(CN)6.pH2O. The method also forms an activated carbon anode and a membrane separating the cathode from the anode, permeable to A and A′ cations. Finally, an electrolyte is added with a metal salt including A′ cations. The electrolyte may be aqueous.
摘要翻译：超级电容器具有制造超级电容器的方法。该方法提供具有化学式AmM1xM2y（CN）6.pH2O的干燥的六氰基金属盐颗粒与普鲁士蓝六氰基金属酸盐晶体结构，其中A是碱金属或碱土金属阳离子，M1和M2是具有2+或3+价态的金属职位变量m在0.5至2的范围内，x在0.5至1.5的范围内，y在0.5至1.5的范围内，p在0至6的范围内。六氰基金属盐颗粒与粘合剂和电子导体粉末，以形成包含AmM1xM2y（CN )6pH2O的阴极。该方法还形成活性炭阳极和将阴极与阳极分开的膜，其可透过A和A'阳离子。最后，向电解质中加入包含A'阳离子的金属盐。电解质可以是水性的。

78. 发明申请

US20140255770A1 Carbon-Sulfur Composite Cathode Passivation and Method for Making Same 审中-公开
标题翻译：碳硫复合阴极钝化及其制备方法
公开(公告)号：US20140255770A1
公开(公告)日：2014-09-11
申请号：US13793559
申请日：2013-03-11
申请人： Jong-Jan Lee , Sean Andrew Vail
发明人： Jong-Jan Lee , Sean Andrew Vail
IPC分类号： H01M4/36 , H01M4/1393 , H01M4/04
CPC分类号： H01M4/366 , H01M4/0404 , H01M4/133 , H01M4/136 , H01M4/1393 , H01M4/1397 , H01M4/62 , H01M10/052
摘要： A method is provided for forming a carbon-sulfur (C—S) battery cathode. The method forms a C—S nanocomposite material overlying metal current collector. A dielectric is formed overlying the C—S material that is permeable to lithium (Li) ions and electrolyte, but impermeable to polysulfides. Typically, the C—S nanocomposite material is porous and the dielectric forms a uniform coating of dielectric inside C—S nanocomposite pores. The dielectric includes a metal (M) oxide with an oxy bridge formation (M-O-M). The metal (M) may, for example, be Mg, Al, Si, Ti, Zn, In, Sn, Mn, Ni, or Cu. A C—S battery cathode, and a battery with a C—S are also provided.
摘要翻译：提供了形成碳 - 硫（C-S）电池阴极的方法。该方法形成了覆盖金属集电器的C-S纳米复合材料。形成电介质覆盖可透过锂（Li）离子和电解质但对多硫化物不渗透的C-S材料。通常，C-S纳米复合材料是多孔的，并且电介质在C-S纳米复合材料孔内形成均匀的电介质涂层。电介质包括具有氧桥形成（M-O-M）的金属（M）氧化物。金属（M）可以是例如Mg，Al，Si，Ti，Zn，In，Sn，Mn，Ni或Cu。还提供C-S电池阴极和具有C-S的电池。

79. 发明授权

US08809113B2 Solution-processed metal-selenide semiconductor using selenium nanoparticles 有权
标题翻译：使用硒纳米粒子的溶液处理的金属硒化物半导体
公开(公告)号：US08809113B2
公开(公告)日：2014-08-19
申请号：US13674005
申请日：2012-11-10
申请人： Sean Andrew Vail , Alexey Koposov , Jong-Jan Lee
发明人： Sean Andrew Vail , Alexey Koposov , Jong-Jan Lee
IPC分类号： H01L31/032 , C09D11/00 , B82Y30/00 , B82Y40/00
CPC分类号： H01L31/0326 , B82Y30/00 , B82Y40/00 , C09D11/00 , C09D11/005 , C09D11/54 , H01L21/02425 , H01L21/02568 , H01L21/02601 , H01L21/02614 , H01L21/02628 , H01L31/0322 , Y02E10/541
摘要： A method is provided for forming a solution-processed metal and mixed-metal selenide semiconductor using selenium (Se) nanoparticles (NPs). The method forms a first solution including SeNPs dispersed in a solvent. Added to the first solution is a second solution including a first material set of metal salts, metal complexes, or combinations thereof, which are dissolved in a solvent, forming a third solution. The third solution is deposited on a conductive substrate, forming a first intermediate film comprising metal precursors, from corresponding members of the first material set, and embedded SeNPs. As a result of thermally annealing, the metal precursors are transformed and the first intermediate film is selenized, forming a first metal selenide-containing semiconductor. In one aspect, the first solution further comprises ligands for the stabilization of SeNPs, which are liberated during thermal annealing. In another aspect, the metal selenide-containing semiconductor comprises copper, indium, gallium diselenide (CIGS).
摘要翻译：提供了使用硒（Se）纳米颗粒（NP）形成溶液处理金属和混合金属硒化物半导体的方法。该方法形成包含分散在溶剂中的SeNP的第一溶液。添加到第一溶液中是第二溶液，其包括溶解在溶剂中的第一组金属盐，金属络合物或其组合，形成第三溶液。第三溶液沉积在导电基底上，形成包含金属前体的第一中间膜，来自第一材料组的相应构件和嵌入的SeNP。作为热退火的结果，金属前体被转化并且第一中间膜被硒化，形成第一含金属硒化物的半导体。在一个方面，第一溶液还包含用于稳定SeNP的配体，其在热退火期间释放。另一方面，含金属硒化物的半导体包括铜，铟，二硒化镓（CIGS）。

80. 发明申请

US20130291941A1 Solid-State Dye-Sensitized Solar Cell Using Sodium or Potassium Ionic Dopant 审中-公开
标题翻译：固态染料敏化太阳能电池使用钠或钾离子掺杂剂
公开(公告)号：US20130291941A1
公开(公告)日：2013-11-07
申请号：US13461674
申请日：2012-05-01
申请人： Sean Andrew Vail , Wei Pan , Gary D. Foley , Jong-Jan Lee
发明人： Sean Andrew Vail , Wei Pan , Gary D. Foley , Jong-Jan Lee
IPC分类号： H01L31/0256 , H01L31/0264 , H01L31/0376 , B82Y30/00
CPC分类号： H01G9/2009 , B82Y30/00 , H01L51/002 , H01L51/4226 , Y02E10/542 , Y02E10/549
摘要： A solid-state hole transport composite material (ssHTM) is provided made from a p-type organic semiconductor and a dopant material serving as a source for either sodium (Na+) or potassium (K+) ions. The p-type organic semiconductor may be molecular (a collection of discrete molecules, that are either chemically identical or different), oligomeric, polymeric materials, or combinations thereof. In one aspect, the p-type organic semiconductor is 2,2′,7,7′-tetrakis(N,N-di-p-methoxyphenylamine)-9,9′-spirobifluorene (Spiro-OMeTAD). The dopant material is an inorganic or organic material salt. A solid-state dye-sensitized solar cell (ssDSC) with the above-described ssHTM, is also provided.
摘要翻译：提供由p型有机半导体和用作钠（Na +）或钾（K +）离子的源的掺杂剂材料制成的固态空穴传输复合材料（ssHTM）。 p型有机半导体可以是分子（离散分子的集合，其化学上相同或不同），低聚物，聚合材料或其组合。一方面，p型有机半导体是2,2'，7,7'-四（N，N-二 - 对甲氧基苯胺）-9,9'-螺二芴（Spiro-OMeTAD）。掺杂剂材料是无机或有机材料盐。还提供了具有上述ssHTM的固态染料敏化太阳能电池（ssDSC）。

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