专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US5640040A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5640040A
公开(公告)日：1997-06-17
申请号：US481097
申请日：1995-06-07
申请人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura , Hideyuki Funaki
发明人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura , Hideyuki Funaki
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861 , H01L23/58
CPC分类号： H01L29/404 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/0834 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L29/78603 , H01L2924/0002
摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer formed on the insulating layer and made of a high resistance semiconductor of a first conductivity type, a first impurity region of the first conductivity type formed in the active layer, and a second impurity region of a second conductivity type formed in the active layer and spaced apart from the first impurity region by a predetermined distance. The first impurity region is formed of diffusion layers. The diffusion layers are superimposed one upon another and differ in diffusion depth or diffusion window width, or both.
摘要翻译：一种高耐压电压半导体器件，包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上并由第一导电类型的高电阻半导体形成的有源层，第一导电类型的第一杂质区形成在有源层中的第二杂质区和形成在有源层中并与第一杂质区隔开预定距离的第二导电类型的第二杂质区。第一杂质区由扩散层形成。扩散层彼此叠加并且扩散深度或扩散窗宽度不同，或两者均不同。

72. 发明授权

US5592014A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5592014A
公开(公告)日：1997-01-07
申请号：US484864
申请日：1995-06-07
申请人： Hideyuki Funaki , Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura
发明人： Hideyuki Funaki , Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura
IPC分类号： H01L21/336 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861 , H01L23/58
CPC分类号： H01L29/404 , H01L21/76264 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L2924/0002
摘要： A high breakdown voltage semiconductor apparatus comprises a substrate having an insulating layer formed thereon, a high resistance semiconductor layer of a first conductivity type formed on said insulating layer, a base region of the first conductivity type formed selectively in a surface region of the high resistance semiconductor layer, a drift region of a second conductivity type formed selectively in the surface region of the high resistance semiconductor layer so as not to reach the insulating layer, a source region of the second conductivity type formed in the base region, a drain region formed in the drift region, a gate electrode formed on a region between the source region and the drift region, with a gate insulating film interposed between the gate electrode and the region between the source region and the drift region, a source electrode provided in contact with the base region and the source region, a drain electrode provided in contact with the drain region. The dosage of impurities in the high resistance semiconductor layer is 2.times.10.sup.12 cm.sup.-2 to 3.times.10.sup.12 cm.sup.-2 and the dosage of impurities in the drift layer is 1.times.10.sup.12 cm.sup.-2 to 2.times.10.sup.12 cm.sup.-2.
摘要翻译：一种高耐压电压半导体装置，包括：在其上形成有绝缘层的基板，形成在所述绝缘层上的第一导电类型的高电阻半导体层，所述第一导电类型的基极区选择性地形成在所述高电阻的表面区域中半导体层，选择性地形成在高电阻半导体层的表面区域中以便不到达绝缘层的第二导电类型的漂移区域，形成在基极区域中的第二导电类型的源极区域，形成的漏极区域在漂移区域中，形成在源极区域和漂移区域之间的区域上的栅电极，栅极绝缘膜插入在栅极电极和源极区域与漂移区域之间的区域中，源极电极与所述基极区域和所述源极区域，设置成与所述漏极区域接触的漏极电极。高电阻半导体层中的杂质用量为2×10 12 cm -2至3×10 12 cm -2，漂移层中的杂质用量为1×10 12 cm -2至2×10 12 cm -2。

73. 发明授权

US5554862A Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US5554862A
公开(公告)日：1996-09-10
申请号：US183364
申请日：1994-01-19
申请人： Ichiro Omura , Mitsuhiko Kitagawa , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Ichiro Omura , Mitsuhiko Kitagawa , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/745 , H01L29/749 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/749
摘要： In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.
摘要翻译：在功率半导体器件中，在p发射极层上形成n基极。在n基层上，横向形成p基层，n发射极层和高浓度p层。在p基层中，n型源层与n型发射极层隔开规定的距离。在n-发射极层中，与高浓度p层隔开规定的距离形成p源层。在由n源层和n发射极层夹在的区域上经由第一栅极绝缘膜形成第一栅电极。在由高浓度p层和p源层夹着的区域上经由第二栅极绝缘膜形成第二栅电极。在p发射极层上形成第一主电极。第二主电极形成为与p基层，n源层和p源层接触。

74. 发明授权

US07915617B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07915617B2
公开(公告)日：2011-03-29
申请号：US11478623
申请日：2006-07-03
申请人： Tsuneo Ogura , Ichiro Omura
发明人： Tsuneo Ogura , Ichiro Omura
IPC分类号： H01L31/0312
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0619 , H01L29/0696 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/1033 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/66068 , H01L29/7397 , H01L29/7813 , H01L29/7828
摘要： A semiconductor device comprises: a first semiconductor layer of silicon carbide of a first conductivity type; a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer; a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer; a gate insulating film provided on the second semiconductor layer; a gate electrode formed on the gate insulating film; and a third semiconductor layer of the first conductivity type intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode. The third semiconductor layer is selectively provided on the first semiconductor layer and is adjacent to the second semiconductor layer. A doping density of the third semiconductor layer is higher than a doping density of the first semiconductor layer.
摘要翻译：半导体器件包括：第一导电类型的碳化硅的第一半导体层; 选择性地设置在所述第一半导体层上的第二导电类型的碳化硅的第二半导体层; 选择性地设置在第二半导体层上的第一导电类型的碳化硅主电极层; 设置在所述第二半导体层上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及第一导电类型的第三半导体层，当在栅电极施加导通电压时，插入形成在主电极层和第一半导体层之间的电流路径。第三半导体层选择性地设置在第一半导体层上并与第二半导体层相邻。第三半导体层的掺杂浓度高于第一半导体层的掺杂密度。

75. 发明授权

US07864021B2 Integrated circuit device 失效
标题翻译：集成电路器件
公开(公告)号：US07864021B2
公开(公告)日：2011-01-04
申请号：US12269396
申请日：2008-11-12
申请人： Kenichi Matsushita , Ichiro Omura
发明人： Kenichi Matsushita , Ichiro Omura
IPC分类号： H01F27/28 , H01F5/00 , G05F1/00
CPC分类号： H01F17/0033 , H01F27/402 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes: a main interconnect; and a coil located on one side of the main interconnect at a position fixed with respect to the main interconnect, the coil having a central axis extending in a direction crossing the extending direction of the main interconnect. An induction current detectable by the coil is generated due to a current flowing through the main interconnect.
摘要翻译：集成电路装置包括：主互连; 以及位于所述主互连的一侧上的线圈，所述线圈相对于所述主互连固定，所述线圈具有沿与所述主互连的延伸方向交叉的方向延伸的中心轴线。由于电流流过主互连线，可以产生由线圈检测到的感应电流。

76. 发明授权

US07772641B2 Power semiconductor device with a plurality of gate electrodes 有权
标题翻译：具有多个栅电极的功率半导体器件
公开(公告)号：US07772641B2
公开(公告)日：2010-08-10
申请号：US11682670
申请日：2007-03-06
申请人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
发明人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
IPC分类号： H01L29/80
CPC分类号： H01L29/7397 , H01L23/4824 , H01L29/0619 , H01L29/0696 , H01L29/41775 , H01L29/4236 , H01L29/66348 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
摘要翻译：功率半导体器件包括：半导体层，具有沿条形配置沿着第一方向延伸的沟槽; 掩埋在所述沟槽中的用于控制在所述半导体层中流动的电流的栅电极; 以及由具有比栅极电极更高的导电性的材料制成的栅极插塞，栅极插塞具有带状结构，并沿第一方向连接到栅电极。半导体层包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层，部分地设置在第一半导体层的上表面上; 第一导电类型的第三半导体层部分地设置在第二半导体层上; 以及设置在第一半导体层的下表面上的第二导电类型的第四半导体层。

77. 发明授权

US07732837B2 Nitride semiconductor device 失效
标题翻译：氮化物半导体器件
公开(公告)号：US07732837B2
公开(公告)日：2010-06-08
申请号：US11766484
申请日：2007-06-21
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/06
CPC分类号： H01L29/66462 , H01L29/0692 , H01L29/1066 , H01L29/2003 , H01L29/7786
摘要： In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.
摘要翻译：在根据本发明的一个实施方案的氮化物半导体器件中，在未掺杂的或未掺杂的或未掺杂的氮化物半导体器件上形成电连接到源电极并相对于栅电极延伸并突出到漏极侧的p型氮化镓（GaN） n型氮化镓铝（AlGaN）层作为阻挡层。

78. 发明申请

US20090095977A1 VERTICAL SEMICONDUCTOR DEVICE 有权
标题翻译：垂直半导体器件
公开(公告)号：US20090095977A1
公开(公告)日：2009-04-16
申请号：US12209690
申请日：2008-09-12
申请人： Masanori TSUKUDA , Ichiro Omura
发明人： Masanori TSUKUDA , Ichiro Omura
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0619
摘要： In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer of the first conductivity type, a collector layer of the second conductivity type and a collector electrode which are formed at the other main surface of the first base layer, an electric field relaxing structure selectively formed outside from the second base layers and the collector layer is formed expect the region below the electric field relaxing structure.
摘要翻译：在包括第一导电类型的第一基底层，第二导电类型的第二基底层，第一导电类型的发射极层和形成在第一基底层的一个主表面处的栅电极的垂直半导体器件中，第一导电类型的缓冲层，第二导电类型的集电极层和形成在第一基极层的另一个主表面上的集电极，选择性地从第二基极层和集电体形成的电场缓和结构形成层希望低于电场松弛结构的区域。

79. 发明授权

US07514783B2 Semiconductor module 失效
公开(公告)号：US07514783B2
公开(公告)日：2009-04-07
申请号：US11214730
申请日：2005-08-31
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H01L23/34
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

80. 发明授权

US07462909B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07462909B2
公开(公告)日：2008-12-09
申请号：US11453997
申请日：2006-06-16
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： First semiconductor pillar layers of a first conduction type and second semiconductor pillar layers of a second conduction type are arranged on a first semiconductor layer of the first conduction type laterally, periodically and alternately at a first period to form a first pillar layer. Third semiconductor pillar layers of the first conduction type and fourth semiconductor pillar layers of the second conduction type are arranged on the first pillar layer laterally, periodically and alternately at a second period smaller than the first period to form a second pillar layer. A semiconductor base layer of the second conduction type is formed on a surface of the fourth semiconductor pillar layer. A semiconductor diffused layer of the first conduction type is formed on a surface of the semiconductor base layer.
摘要翻译：第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层被布置在第一导电类型的第一半导体层上，在第一周期上周期性地和周期性地交替地形成第一柱层。第二导电类型的第一导电类型的第三半导体柱层和第二导电类型的第四半导体柱层在第一柱层上以比第一周期小的周期性地交替布置在第一柱层上，以形成第二柱层。在第四半导体柱层的表面上形成第二导电类型的半导体基底层。在半导体基底层的表面上形成第一导电类型的半导体扩散层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式