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71. 发明申请

US20110086490A1 SINGLE-SIDE IMPLANTING PROCESS FOR CAPACITORS OF STACK DRAM 审中-公开
标题翻译：堆叠DRAM电容单面贴装工艺
公开(公告)号：US20110086490A1
公开(公告)日：2011-04-14
申请号：US12720977
申请日：2010-03-10
申请人： HSIAO-LEI WANG , SHIN BIN HUANG , CHING-NAN HSIAO , CHUNG-LIN HUANG
发明人： HSIAO-LEI WANG , SHIN BIN HUANG , CHING-NAN HSIAO , CHUNG-LIN HUANG
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/31111 , H01L27/10852
摘要： A single-side implanting process for capacitors of stack DRAM is disclosed. Firstly, form a stacked structure with a dielectric layer and an insulating nitride layer on a semi-conductor substrate and etch the stacked structure to form a plurality of trenches. Then, form conductive metal plates respectively on an upper surface of the stacked structure and bottoms of the trenches, form a continuous conductive nitride film, form a continuous oxide film, and form a photo resist layer for covering the trenches which are provided for isolation. Then, form a plurality of implanted oxide areas on a single-side surface, remove the photo resist layer, remove the plurality of implanted oxide areas, remove the conductive metal plates and the conductive nitride film uncovered by the oxide film, and remove the oxide film and the dielectric film.
摘要翻译：公开了用于堆叠DRAM的电容器的单侧注入工艺。首先，在半导体基板上形成具有介电层和绝缘氮化物层的堆叠结构，并蚀刻该层叠结构以形成多个沟槽。然后，分别在层叠结构的上表面和沟槽的底部形成导电性金属板，形成连续的导电性氮化物膜，形成连续的氧化膜，形成用于覆盖设置用于隔离的沟槽的光致抗蚀剂层。然后，在单面表面上形成多个注入的氧化物区域，去除光致抗蚀剂层，去除多个注入的氧化物区域，去除未被氧化膜覆盖的导电金属板和导电氮化物膜，并除去氧化物薄膜和电介质薄膜。

72. 发明申请

US20110084325A1 DRAM STRUCTURE WITH A LOW PARASITIC CAPACITANCE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：具有低的PARASIIC电容的DRAM结构及其制造方法
公开(公告)号：US20110084325A1
公开(公告)日：2011-04-14
申请号：US12649361
申请日：2009-12-30
申请人： Hsiao-Lei Wang , Chung-Lin Huang , Hung-Chang Liao , Shih-Lung Chen
发明人： Hsiao-Lei Wang , Chung-Lin Huang , Hung-Chang Liao , Shih-Lung Chen
IPC分类号： H01L27/108 , H01L21/762
CPC分类号： H01L27/10894 , H01L21/76229 , H01L27/10897
摘要： An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization.
摘要翻译：描述了一种用于堆叠DRAM栅极堆叠的氧化物间隔物，包括：具有存储器阵列区域和外围区域的半导体衬底，分别设置在存储器阵列区域和外围区域内的多个栅极，设置在栅极上的氧化硅间隔物其中多晶硅接触插塞通过多晶硅沉积和化学机械抛光形成。在形成多晶硅接触塞之后，沉积氧化硅层以隔离触点和栅极。通过化学机械抛光去除接触塞顶部的氧化硅层，实现平面化。

73. 发明授权

US07855124B2 Method for forming a semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07855124B2
公开(公告)日：2010-12-21
申请号：US12035529
申请日：2008-02-22
申请人： Hung-Ming Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Ming Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/76
CPC分类号： H01L21/823437 , H01L21/28273 , H01L21/823468 , H01L21/823481 , H01L27/11521
摘要： A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer.
摘要翻译：一种形成半导体器件的方法，包括以下步骤：提供衬底; 在所述衬底上形成图案化的叠层，所述衬底上包括在所述衬底上的第一电介质层，所述第一电介质层上的第一导电层和所述第一导电层上的掩模层，其中所述掩模层的宽度小于所述第一导电层的宽度导电层; 在所述图案化叠层的侧壁上形成第二电介质层; 在所述基板上形成第三电介质层; 在所述衬底上形成第二导电层; 以及去除所述掩模层和由所述掩模层覆盖的所述第一导电层的一部分以形成开口以部分地暴露所述第一导电层。

74. 发明申请

US20100279499A1 METHOD FOR MANUFACTURING A MEMORY 有权
标题翻译：制造存储器的方法
公开(公告)号：US20100279499A1
公开(公告)日：2010-11-04
申请号：US12839387
申请日：2010-07-19
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.
摘要翻译：一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

75. 发明授权

US07781804B2 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07781804B2
公开(公告)日：2010-08-24
申请号：US12101164
申请日：2008-04-11
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L29/80
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.
摘要翻译：设置在基板上的非易失性存储器包括有源区，存储器阵列和触点。由设置在基板中的隔离结构限定的有源区域沿第一方向延伸。存储器阵列设置在衬底上，并且包括存储单元列，控制栅极线和选择栅极线。每个存储单元列包括彼此串联的存储单元和设置在存储单元外部的衬底中的源/漏区。触点在存储器阵列的一侧设置在衬底上，并沿第二方向布置。第二个方向穿过第一个方向。每个触点延伸穿过隔离结构，并且在每个相邻的活性区域的每两个处连接衬底中的源极/漏极区域。

76. 发明申请

US20100013062A1 NONVOLATILE MEMORY CELL 有权
标题翻译：非易失性存储单元
公开(公告)号：US20100013062A1
公开(公告)日：2010-01-21
申请号：US12244295
申请日：2008-10-02
申请人： Shin-Bin Huang , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Shin-Bin Huang , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L23/58 , H01L21/31
CPC分类号： H01L27/11521 , H01L21/3185 , H01L29/42324 , H01L29/66825
摘要： A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.
摘要翻译：提供非易失性存储单元。提供半导体衬底。导电层和间隔层顺序地设置在半导体衬底之上。在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。第一氧化物层形成在沟槽的底部。在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。在沟槽中形成第一多晶硅层。并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。

77. 发明授权

US07576381B2 Memory structure and fabricating method thereof 有权
标题翻译：存储器结构及其制造方法
公开(公告)号：US07576381B2
公开(公告)日：2009-08-18
申请号：US11955397
申请日：2007-12-13
申请人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
发明人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
IPC分类号： H01L27/108
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/42336
摘要： A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.
摘要翻译：提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。衬底具有沟槽，其中。第一介电层设置在沟槽的内表面上。第一导电层设置在沟槽下部的第一电介质层上。第二导电层设置在第一导电层上方并填充沟槽。第二电介质层设置在第一导电层和第二导电层之间。间隔物设置在第一介电层和第二导电层之间。掺杂区域设置在沟槽侧面的衬底中。

78. 发明申请

US20090061581A1 METHOD FOR MANUFACTURING TRENCH ISOLATION STRUCTURE AND NON-VOLATILE MEMORY 有权
标题翻译：制造分离结构和非易失性存储器的方法
公开(公告)号：US20090061581A1
公开(公告)日：2009-03-05
申请号：US11945199
申请日：2007-11-26
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.
摘要翻译：提供一种用于制造非易失性存储器的方法。在衬底中形成的沟槽中形成隔离结构。去除隔离结构的一部分以形成凹部。在基板上依次形成第一介电层和第一导电层。在基板上形成棒状盖层。未被棒状帽层覆盖的第一导电层被去除以形成第一栅极结构。在第一栅极结构的侧壁上形成第二介电层。在第一栅极结构之间的衬底上形成第三电介质层。在第三电介质层上形成第二导电层。条形盖层和第一导电层的一部分被去除以形成第二栅极结构。在每个第二栅极结构的两侧在衬底中形成掺杂区域。

79. 发明申请

US20090014773A1 TWO BIT MEMORY STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：两位存储器结构及其制造方法
公开(公告)号：US20090014773A1
公开(公告)日：2009-01-15
申请号：US11946868
申请日：2007-11-29
申请人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
发明人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
IPC分类号： H01L29/78 , H01L21/76
CPC分类号： H01L29/7881 , H01L29/66825
摘要： A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.
摘要翻译：一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层，第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽用第二导电层打开，并移除垫。

80. 发明申请

US20080305593A1 MEMORY STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：记忆结构及其制作方法
公开(公告)号：US20080305593A1
公开(公告)日：2008-12-11
申请号：US11949786
申请日：2007-12-04
申请人： Ching-Nan Hsiao , Pei-Ing Lee , Ming-Cheng Chang , Chung-Lin Huang , Hsi-Hua Chang , Chih-Hsiang Wu
发明人： Ching-Nan Hsiao , Pei-Ing Lee , Ming-Cheng Chang , Chung-Lin Huang , Hsi-Hua Chang , Chih-Hsiang Wu
IPC分类号： H01L21/336
CPC分类号： H01L27/11534 , H01L21/84 , H01L27/11526 , H01L29/42336 , H01L29/66825 , H01L29/7887
摘要： A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.
摘要翻译：本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。然后，在第一凹槽上形成第一栅极电介质层。第一导电层形成在第一栅极介电层上。之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。在第一凹槽的底部形成第二凹槽。在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。形成为填充第一和第二凹槽的第二导电层。

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