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1. 发明授权

US07714445B2 Dynamic random access memory with an electrostatic discharge structure and method for manufacturing the same 有权
标题翻译：具有静电放电结构的动态随机存取存储器及其制造方法
公开(公告)号：US07714445B2
公开(公告)日：2010-05-11
申请号：US11951274
申请日：2007-12-05
申请人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
发明人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
IPC分类号： H01L23/552 , H01L21/768
CPC分类号： H01L27/0251 , H01L27/10894
摘要： The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.
摘要翻译：本发明提供一种具有静电放电（ESD）区域的动态随机存取存储器（DRAM）。 ESD插头的上部是金属，ESD插头的下部是多晶硅。该结构可以提高ESD区域的机械强度并增强静电放电的导热性。此外，可以减少ESD插头和基板之间的接触面积，而不增加ESD插头的纵横比。所描述的结构由低临界尺寸控制的图案化光致抗蚀剂完成，使得工艺和设备基本上保持而不会大幅变化。

2. 发明授权

US07700991B2 Two bit memory structure and method of making the same 有权
标题翻译：两位存储器结构和制作方法相同
公开(公告)号：US07700991B2
公开(公告)日：2010-04-20
申请号：US11946868
申请日：2007-11-29
申请人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
发明人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , H01L29/66825
摘要： A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.
摘要翻译：一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层，第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽用第二导电层打开，并移除垫。

3. 发明申请

US20090014886A1 DYNAMIC RANDOM ACCESS MEMORY WITH AN ELECTROSTATIC DISCHARGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：具有静电放电结构的动态随机存取存储器及其制造方法
公开(公告)号：US20090014886A1
公开(公告)日：2009-01-15
申请号：US11951274
申请日：2007-12-05
申请人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
发明人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
IPC分类号： H01L23/522 , H01L21/768 , H02H9/00
CPC分类号： H01L27/0251 , H01L27/10894
摘要： The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.
摘要翻译：本发明提供一种具有静电放电（ESD）区域的动态随机存取存储器（DRAM）。 ESD插头的上部是金属，ESD插头的下部是多晶硅。该结构可以提高ESD区域的机械强度并增强静电放电的导热性。此外，可以减少ESD插头和基板之间的接触面积，而不增加ESD插头的纵横比。所描述的结构由低临界尺寸控制的图案化光致抗蚀剂完成，使得工艺和设备基本上保持而不会大幅变化。

4. 发明授权

US07576381B2 Memory structure and fabricating method thereof 有权
标题翻译：存储器结构及其制造方法
公开(公告)号：US07576381B2
公开(公告)日：2009-08-18
申请号：US11955397
申请日：2007-12-13
申请人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
发明人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
IPC分类号： H01L27/108
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/42336
摘要： A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.
摘要翻译：提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。衬底具有沟槽，其中。第一介电层设置在沟槽的内表面上。第一导电层设置在沟槽下部的第一电介质层上。第二导电层设置在第一导电层上方并填充沟槽。第二电介质层设置在第一导电层和第二导电层之间。间隔物设置在第一介电层和第二导电层之间。掺杂区域设置在沟槽侧面的衬底中。

5. 发明申请

US20090014773A1 TWO BIT MEMORY STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：两位存储器结构及其制造方法
公开(公告)号：US20090014773A1
公开(公告)日：2009-01-15
申请号：US11946868
申请日：2007-11-29
申请人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
发明人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
IPC分类号： H01L29/78 , H01L21/76
CPC分类号： H01L29/7881 , H01L29/66825
摘要： A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.
摘要翻译：一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层，第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽用第二导电层打开，并移除垫。

6. 发明申请

US20080265302A1 MEMORY STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：记忆结构及其制作方法
公开(公告)号：US20080265302A1
公开(公告)日：2008-10-30
申请号：US11955397
申请日：2007-12-13
申请人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
发明人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chung-Lin Huang , Shih-Yang Chiu
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/42336
摘要： A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.
摘要翻译：提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。衬底具有沟槽，其中。第一介电层设置在沟槽的内表面上。第一导电层设置在沟槽下部的第一电介质层上。第二导电层设置在第一导电层上方并填充沟槽。第二电介质层设置在第一导电层和第二导电层之间。间隔物设置在第一介电层和第二导电层之间。掺杂区域设置在沟槽侧面的衬底中。

7. 发明授权

US07005701B2 Method for fabricating a vertical NROM cell 有权
标题翻译：制造垂直NROM电池的方法
公开(公告)号：US07005701B2
公开(公告)日：2006-02-28
申请号：US10318551
申请日：2002-12-13
申请人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
发明人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
IPC分类号： H01L29/76 , H01L39/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.
摘要翻译：一种用于制造垂直氮化物只读存储器（NROM）单元的方法。提供具有至少一个沟槽的衬底。间隔件形成在沟槽的侧壁上。随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。在每个掺杂区域上形成位线氧化物。在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

8. 发明授权

US06916715B2 Method for fabricating a vertical NROM cell 有权
标题翻译：制造垂直NROM电池的方法
公开(公告)号：US06916715B2
公开(公告)日：2005-07-12
申请号：US10694155
申请日：2003-10-27
申请人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
发明人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L27/148
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.
摘要翻译：一种用于制造垂直氮化物只读存储器（NROM）单元的方法。提供具有至少一个沟槽的衬底。间隔件形成在沟槽的侧壁上。随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。在每个掺杂区域上形成位线氧化物。在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

9. 发明授权

US07868377B2 Layout and structure of memory 有权
标题翻译：内存布局和结构
公开(公告)号：US07868377B2
公开(公告)日：2011-01-11
申请号：US11927616
申请日：2007-10-29
申请人： Shin-Bin Huang , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Shin-Bin Huang , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.
摘要翻译：提供闪存。具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅晶体管的选通栅极的栅极导体线之间的空间。因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。耗尽模式的选择栅晶体管总是导通。

10. 发明授权

US07682902B2 Memory structure and method of making the same 有权
标题翻译：内存结构和制作方法
公开(公告)号：US07682902B2
公开(公告)日：2010-03-23
申请号：US11949786
申请日：2007-12-04
申请人： Ching-Nan Hsiao , Pei-Ing Lee , Ming-Cheng Chang , Chung-Lin Huang , Hsi-Hua Chang , Chih-Hsiang Wu
发明人： Ching-Nan Hsiao , Pei-Ing Lee , Ming-Cheng Chang , Chung-Lin Huang , Hsi-Hua Chang , Chih-Hsiang Wu
IPC分类号： H01L21/336
CPC分类号： H01L27/11534 , H01L21/84 , H01L27/11526 , H01L29/42336 , H01L29/66825 , H01L29/7887
摘要： A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.
摘要翻译：本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。然后，在第一凹槽上形成第一栅极电介质层。第一导电层形成在第一栅极介电层上。之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。在第一凹槽的底部形成第二凹槽。在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。形成为填充第一和第二凹槽的第二导电层。

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