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1. 发明申请

US20100279472A1 MANUFACTURING METHOD OF NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的制造方法
公开(公告)号：US20100279472A1
公开(公告)日：2010-11-04
申请号：US12838495
申请日：2010-07-19
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/8239
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.
摘要翻译：在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。包括存储单元列的第一存储器阵列形成在衬底上。每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨过存储器单元延伸的控制栅极线列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

2. 发明授权

US07713820B2 Method for manufacturing non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US07713820B2
公开(公告)日：2010-05-11
申请号：US11945199
申请日：2007-11-26
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.
摘要翻译：提供一种用于制造非易失性存储器的方法。在衬底中形成的沟槽中形成隔离结构。去除隔离结构的一部分以形成凹部。在基板上依次形成第一介电层和第一导电层。在基板上形成棒状盖层。未被棒状帽层覆盖的第一导电层被去除以形成第一栅极结构。在第一栅极结构的侧壁上形成第二介电层。在第一栅极结构之间的衬底上形成第三电介质层。在第三电介质层上形成第二导电层。条形盖层和第一导电层的一部分被去除以形成第二栅极结构。在每个第二栅极结构的两侧在衬底中形成掺杂区域。

3. 发明授权

US07781279B2 Method for manufacturing a memory 有权
标题翻译：存储器制造方法
公开(公告)号：US07781279B2
公开(公告)日：2010-08-24
申请号：US12018209
申请日：2008-01-23
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521
摘要： A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.
摘要翻译：一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

4. 发明申请

US20090127610A1 NON-VOLATILE MEMORY AND THE MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20090127610A1
公开(公告)日：2009-05-21
申请号：US12101164
申请日：2008-04-11
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.
摘要翻译：设置在基板上的非易失性存储器包括有源区，存储器阵列和触点。由设置在基板中的隔离结构限定的有源区域沿第一方向延伸。存储器阵列设置在衬底上，并且包括存储单元列，控制栅极线和选择栅极线。每个存储单元列包括彼此串联的存储单元和设置在存储单元外部的衬底中的源/漏区。触点在存储器阵列的一侧设置在衬底上，并沿第二方向布置。第二个方向穿过第一个方向。每个触点延伸穿过隔离结构，并且在每个相邻的活性区域的每两个处连接衬底中的源极/漏极区域。

5. 发明申请

US20090047765A1 METHOD OF MANUFACTURING NON-VOLATILE MEMORY 审中-公开
标题翻译：制造非易失性存储器的方法
公开(公告)号：US20090047765A1
公开(公告)日：2009-02-19
申请号：US11955393
申请日：2007-12-13
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of manufacturing a non-volatile memory is provided. In the method, a first dielectric layer, a first conductive layer, and a first cap layer are formed sequentially on a substrate. The first cap layer and the first conductive layer are patterned to form first gate structures. A second dielectric layer is formed on the sidewall of the first gate structures, and a portion of the first dielectric layer is removed to expose the substrate between the first gate structures. An epitaxy layer is formed on the substrate between two first gate structures. A third dielectric layer is formed on the epitaxy layer. A second conductive layer is formed on the third dielectric layer. The first cap layer and a portion of the first conductive layer are removed to form second gate structures. Finally, a doped region is formed in the substrate at two sides of the second gate structures.
摘要翻译：提供一种制造非易失性存储器的方法。在该方法中，在基板上依次形成第一介电层，第一导电层和第一盖层。图案化第一盖层和第一导电层以形成第一栅极结构。在第一栅极结构的侧壁上形成第二介电层，并且去除第一介电层的一部分以在第一栅极结构之间露出衬底。在两个第一栅极结构之间的衬底上形成外延层。在外延层上形成第三介电层。在第三电介质层上形成第二导电层。去除第一盖层和第一导电层的一部分以形成第二栅极结构。最后，在第二栅极结构的两侧在衬底中形成掺杂区域。

6. 发明授权

US08105900B2 Manufacturing method of non-volatile memory 有权
标题翻译：非易失性存储器的制造方法
公开(公告)号：US08105900B2
公开(公告)日：2012-01-31
申请号：US12838495
申请日：2010-07-19
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.
摘要翻译：在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。包括存储单元列的第一存储器阵列形成在衬底上。每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨越存储器单元延伸的控制栅极线列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

7. 发明授权

US07642191B2 Method of forming semiconductor structure 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07642191B2
公开(公告)日：2010-01-05
申请号：US12019260
申请日：2008-01-24
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/311
CPC分类号： H01L21/823481 , H01L21/823437 , H01L27/115 , H01L27/11521
摘要： A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate, Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer.
摘要翻译：提供一种形成半导体结构的方法。该方法包括提供衬底并在衬底上形成掩模层。接下来，在掩模层和衬底中形成介电隔离，其中介电隔离物延伸到衬底上方。然后，去除掩模层以露出衬底的一部分，并且在衬底的暴露部分上形成电介质层。随后，在电介质层上形成第一导电层，去除介电隔离的一部分，其中绝缘隔离的顶表面低于第一导电层的顶表面。此外，在衬底上形成保形层，并且在保形层上形成第二导电层。

8. 发明申请

US20090087975A1 METHOD FOR MANUFACTURING A MEMORY 有权
标题翻译：制造存储器的方法
公开(公告)号：US20090087975A1
公开(公告)日：2009-04-02
申请号：US12018209
申请日：2008-01-23
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/3205
CPC分类号： H01L27/11521
摘要： A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.
摘要翻译：一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

9. 发明申请

US20090065846A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20090065846A1
公开(公告)日：2009-03-12
申请号：US11955396
申请日：2007-12-13
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7887
摘要： A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure.
摘要翻译：非易失性存储器的制造方法包括在衬底上依次形成第一电介质层，第一导电层和第一覆盖层，以形成第一栅极结构; 在基底上保形地形成第二电介质层; 在每个第一栅极结构的每个侧壁上形成具有比第二介电层更大的湿蚀刻速率的第一间隔物; 部分地去除第一和第二电介质层以暴露衬底。在第一栅极结构之间的衬底上形成第三电介质层; 去除第一间隔物; 在所述第三介电层上形成第二导电层; 移除所述第一盖层和所述第一导电层的一部分以形成第二栅极结构; 以及在每个第二栅极结构的两侧在衬底中形成掺杂区域。

10. 发明授权

US07972924B2 Method for manufacturing a memory 有权
标题翻译：存储器制造方法
公开(公告)号：US07972924B2
公开(公告)日：2011-07-05
申请号：US12839387
申请日：2010-07-19
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/11521
摘要： A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.
摘要翻译：一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

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