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61. 发明授权

US09312221B2 Variable capacitance devices 有权
标题翻译：可变电容器件
公开(公告)号：US09312221B2
公开(公告)日：2016-04-12
申请号：US13916620
申请日：2013-06-13
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hsiao-Tsung Yen , Cheng-Wei Luo
IPC分类号： H01L29/93 , H01L23/522 , H01L29/66 , H01L29/8605 , H01L49/02 , H01L27/06
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0682 , H01L28/40 , H01L29/66166 , H01L29/8605 , H01L2924/0002 , H01L2924/00
摘要： A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable resistor includes a gate structure formed over a channel region defined in a doped well formed in a semiconductor substrate. A resistance of the variable resistor is based on a voltage applied to the gate structure, which adjusts a resistance of the channel and a capacitance of the variable capacitance device.
摘要翻译：可变电容器件包括具有与电容器串联耦合的第一电容和可变电阻器的电容器。可变电阻器包括形成在形成在半导体衬底中的掺杂阱中限定的沟道区上的栅极结构。可变电阻器的电阻基于施加到栅极结构的电压，其调节通道的电阻和可变电容器件的电容。

62. 发明授权

US09312009B2 Non-volatile memory and associated memory array, row decoder, column decoder, write buffer and sensing circuit 有权
标题翻译：非易失性存储器和相关存储器阵列，行解码器，列解码器，写缓冲器和感测电路
公开(公告)号：US09312009B2
公开(公告)日：2016-04-12
申请号：US14592477
申请日：2015-01-08
申请人： eMemory Technology Inc.
发明人： Tzu-Neng Lai , Chih-Hao Huang
IPC分类号： G11C7/00 , G11C16/08 , G11C17/16 , G11C17/18 , H01L27/112 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , H01L23/528 , H01L27/06 , H01L29/10 , H01L29/49 , H01L29/93 , H01L27/115 , H03K3/356 , H01L23/525
CPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , G11C17/146 , G11C17/16 , G11C17/18 , G11C29/76 , H01L23/5252 , H01L23/528 , H01L27/0629 , H01L27/11206 , H01L27/11524 , H01L29/1079 , H01L29/4916 , H01L29/93 , H01L2924/0002 , H03K3/356182 , H01L2924/00
摘要： A non-volatile memory includes a memory array, a row decoder, a column decoder, a write buffer and a sensing circuit. The column decoder includes a programming decoder and a reading decoder. The programming decoder is connected with n bit lines of the memory array. The reading decoder is connected with the n bit lines. During a program cycle, a programming control signal set is activated. Consequently, the programming decoder determines a selected memory cell, and a cell current generated by the selected memory cell flows to the write buffer through the programming decoder and a programming data line. During a read cycle, a reading control signal set is activated. Consequently, the reading decoder determines the selected memory cell, and the cell current generated by the selected memory cell flows to the sensing circuit through the reading decoder and a reading data line.
摘要翻译：非易失性存储器包括存储器阵列，行解码器，列解码器，写缓冲器和感测电路。列解码器包括编程解码器和读取解码器。编程解码器与存储器阵列的n位线连接。读取解码器与n位线连接。在编程周期中，编程控制信号组被激活。因此，编程解码器确定所选择的存储单元，并且由所选择的存储器单元产生的单元电流通过编程解码器和编程数据线流向写入缓冲器。在读取周期期间，读取控制信号组被激活。因此，读取解码器确定所选择的存储单元，并且由选择的存储单元产生的单元电流通过读取解码器和读取数据线流到感测电路。

63. 发明授权

US09293485B2 Flexible display device and method for manufacturing the same 有权
标题翻译：柔性显示装置及其制造方法
公开(公告)号：US09293485B2
公开(公告)日：2016-03-22
申请号：US14744586
申请日：2015-06-19
申请人： LG DISPLAY CO., LTD.
发明人： Sang-Cheon Youn , Hyoung-Suk Jin , Chang-Heon Kang , Se-Yeoul Kwon
IPC分类号： H01L27/14 , H01L29/93 , H01L21/76 , H01L21/3205 , H01L27/12 , H01L51/00 , H01L27/32 , H01L23/00
CPC分类号： H01L27/1259 , H01L24/06 , H01L27/124 , H01L27/3276 , H01L27/3288 , H01L27/3297 , H01L51/0097 , H01L2924/12041 , H01L2924/12044 , Y02E10/549 , Y02P70/521 , H01L2924/00
摘要： Discussed is a flexible display device to reduce a width of a bezel. The flexible display device includes a substrate being formed of a flexible material, a plurality of gate lines and a plurality of data lines crossing each other, a plurality of pads formed in a pad area of a non-display area, a plurality of links formed in a link area of the non-display area a plurality of insulation films formed over the entire surface of the substrate, and a first bending hole formed in a bending area of the non-display area, the first bending hole passing through at least one of the insulation films disposed under the link, wherein the bending area is bent such that the pads are disposed on the lower surface of the substrate.
摘要翻译：讨论的是一种灵活的显示设备来减少边框的宽度。柔性显示装置包括由柔性材料形成的基板，多条栅极线和彼此交叉的多条数据线，形成在非显示区域的焊盘区域中的多个焊盘，形成多个连接在所述非显示区域的连接区域中形成在所述基板的整个表面上的多个绝缘膜，以及形成在所述非显示区域的弯曲区域中的第一弯曲孔，所述第一弯曲孔穿过至少一个设置在所述连杆下方的绝缘膜，其中所述弯曲区域被弯曲，使得所述焊盘设置在所述基板的下表面上。

64. 发明申请

US20150372155A1 Controllable Integrated Capacitive Device 有权
标题翻译：可控综合电容器件
公开(公告)号：US20150372155A1
公开(公告)日：2015-12-24
申请号：US14675468
申请日：2015-03-31
申请人： STMicroelectronics (Rousset) SAS
发明人： Pascal Fornara , Christian Rivero
IPC分类号： H01L29/93 , H01L23/04 , H01L23/528 , H01L23/532 , H01L23/522 , H01L27/06
CPC分类号： H01L23/04 , B81B3/0021 , B81B2201/0221 , H01G5/18 , H01L23/5223 , H01L27/0629 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.
摘要翻译：集成电路包括由绝缘区隔开的几个金属化层。在各种金属化水平下产生其壁包括金属部分的中空壳体。可控电容器件包括位于第一金属化水平的中空壳体内的悬挂金属结构，该第一金属化水平包括固定在壳体的两个固定区域上的第一元件和从第一元件以悬臂方式延伸的至少一个第二元件，并且包括第一电极的电容器件。第二电极包括位于与面向第一电极的第一金属化水平相邻的第二金属化水平的第一固定体。第一元件可以从该第一元件的控制区域的弯曲中控制，以便改变两个电极之间的距离。

65. 发明授权

US09117937B2 Group III nitride semiconductor frequency multiplier 有权
标题翻译： III族氮化物半导体倍频器
公开(公告)号：US09117937B2
公开(公告)日：2015-08-25
申请号：US14338598
申请日：2014-07-23
申请人： U.S. Army Research Laboratory
发明人： Pankaj B. Shah , H. Alfred Hung
IPC分类号： H01L31/0256 , H01L29/93 , H01L29/20 , H01L29/872 , H01L29/205 , H01L29/16 , H01L29/22 , H01L29/66
CPC分类号： H01L29/93 , H01L29/1608 , H01L29/2003 , H01L29/205 , H01L29/22 , H01L29/66174 , H01L29/872
摘要： A varactor comprising two Schottky diodes, each diode comprising a substrate and a plurality of layers formed on the substrate including at least one GaN layer and at least one semi-insulating material layer formed of a material with an energy gap greater than 3.5 and free carrier mobility less than 300 cm2/V-s; the Schottky diodes having cathodes adapted to be connected to an AC voltage input and being configured so that as the AC voltage applied to the cathodes increases the capacitance decreases nonlinearly, the nonlinear transition from high capacitance to low capacitance being adjustable by utilizing the intrinsic carrier concentration of the semi-insulating layer to obtain an optimal nonlinear transition for the predetermined AC voltage applied to the cathodes. A method of making a varactor comprising computer modeling to produce capacitance-voltage curves, modifying at least one semi-insulating region, and modeling power input/output efficiency for a predetermined input signal.
摘要翻译：一种包括两个肖特基二极管的变容二极管，每个二极管包括衬底和形成在衬底上的多个层，包括至少一个GaN层和由能隙大于3.5的材料形成的至少一个半绝缘材料层和自由载体迁移率小于300 cm2 / Vs; 肖特基二极管具有适于连接到AC电压输入的阴极并且被配置为使得随着施加到阴极的AC电压增加，电容非线性减小，从高电容到低电容的非线性转变可通过利用本征载流子浓度以获得施加到阴极的预定AC电压的最佳非线性转变。一种制造变容二极管的方法，包括计算机建模以产生电容 - 电压曲线，修改至少一个半绝缘区域，以及为预定输入信号建模功率输入/输出效率。

66. 发明授权

US09019028B2 Integrated epitaxial structure for compound semiconductor devices 有权
标题翻译：用于化合物半导体器件的集成外延结构
公开(公告)号：US09019028B2
公开(公告)日：2015-04-28
申请号：US13661804
申请日：2012-10-26
申请人： WIN Semiconductors Corp.
发明人： Cheng-Kuo Lin , Szu-Ju Li , Rong-Hao Syu , Shu-Hsiao Tsai
IPC分类号： H01L29/205 , H01L29/36 , H01L29/737 , H01L29/812 , H01L29/93 , H01L27/06 , H01L29/20
CPC分类号： H01L29/205 , H01L27/0605 , H01L29/20 , H01L29/36 , H01L29/7371 , H01L29/812 , H01L29/93
摘要： An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.
摘要翻译：公开了一种化合物半导体器件的集成结构。集成结构包括从底部到顶部的衬底，第一外延层，蚀刻停止层，第二外延层，子集电极层，集电极层，基极层和发射极层，其中第一外延层是p型掺杂层，第二外延层是具有逐渐增加或降低的掺杂浓度的n型渐变掺杂层，并且子集电极层是n型掺杂层。该集成结构可用于形成HBT，变容二极管或MESFET。

67. 发明授权

US09018734B2 Single wall carbon nanotube diodes 有权
标题翻译：单壁碳纳米管二极管
公开(公告)号：US09018734B2
公开(公告)日：2015-04-28
申请号：US13442005
申请日：2012-04-09
申请人： Shashi P. Karna , Mark Griep , Govind Mallick
发明人： Shashi P. Karna , Mark Griep , Govind Mallick
IPC分类号： H01L29/93 , H01L51/05 , B82Y40/00 , B82Y10/00 , H01L51/00
CPC分类号： H01L51/0579 , B82Y10/00 , B82Y40/00 , H01L51/0048 , Y10T428/2918
摘要： Methods and devices relating to diodes including single-wall carbon nanotubes (SWCNT) are disclosed according to embodiments of the present invention. According to one embodiment, a diode may include one or more SWCNTs. The SWCNTs may be grouped together in multiple bundles with the SWCNTs being generally aligned parallel to each other in the bundles.
摘要翻译：根据本发明的实施例公开了涉及包括单壁碳纳米管（SWCNT）的二极管的方法和装置。根据一个实施例，二极管可以包括一个或多个SWCNT。 SWCNT可以以多个束组合在一起，其中SWCNT通常在束中彼此平行对齐。

68. 发明授权

US09000866B2 Varactor shunt switches with parallel capacitor architecture 有权
标题翻译：具有并联电容架构的变压器并联开关
公开(公告)号：US09000866B2
公开(公告)日：2015-04-07
申请号：US13533310
申请日：2012-06-26
申请人： Guru Subramanyam
发明人： Guru Subramanyam
IPC分类号： H01L29/93 , H01L27/08 , H01P1/15 , H01P9/00 , H01P3/00
CPC分类号： H01P1/15 , H01L27/0808 , H01P3/003
摘要： A parallel capacitor varactor shunt switch device may include a shunt layer, a coplanar waveguide (CPW) layer, and a tunable thin film dielectric layer that is interposed between the shunt layer and the CPW layer. The tunable thin film dielectric layer electrically isolates the shunt layer from the CPW layer. The shunt layer includes a plurality of parallel shunt lines. The CPW layer includes a CPW signal transmission line with two CPW ground lines parallel to the CPW signal transmission line. A plurality of varactor areas equal in number to the plurality of parallel shunt lines are defined in the CPW signal transmission line, each varactor area corresponding to an overlap of the CPW signal transmission line with a respective shunt line and each respective parallel shunt line and its corresponding varactor area defines a capacitor.
摘要翻译：并联电容器变容二极管分流开关装置可以包括分流层，共面波导（CPW）层和介于分流层和CPW层之间的可调谐薄膜电介质层。可调薄膜电介质层将分流层与CPW层电隔离。并联层包括多个并联分流线。 CPW层包括具有与CPW信号传输线并联的两个CPW接地线的CPW信号传输线。在CPW信号传输线中定义多个与多个并联分流线相等数量的变容二极管区域，每个变容二极管区域对应于CPW信号传输线与相应的分流线和每个相应的并联分流线的重叠，相应的变容二极管区域定义了一个电容器。

69. 发明授权

US08963289B2 Digital semiconductor variable capacitor 有权
标题翻译：数字半导体可变电容器
公开(公告)号：US08963289B2
公开(公告)日：2015-02-24
申请号：US13889317
申请日：2013-05-07
申请人： Fabio Alessio Marino , Paolo Menegoli
发明人： Fabio Alessio Marino , Paolo Menegoli
IPC分类号： H01L29/93 , H01L29/66
CPC分类号： H01L29/93 , H01L29/66174 , H01L29/66189 , H01L29/94
摘要： A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable capacitor with MOS compatible structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the capacitance value between the other two terminals of the device, by increasing or decreasing its DC voltage with respect to one of the main terminals of the device. Furthermore, the present invention decouples the AC signal and the DC control voltage preventing distortion of the RF signal. The present invention describes a controllable capacitor whose capacitance value is not necessarily linear with its control voltage, but although possibly abrupt in its characteristic, is utilized to manufacture a semiconductor variable capacitor with digital control to improve its noise and linearity performance while maintaining high quality factor.
摘要翻译：提出了一种新型的半导体可变电容器。半导体结构简单，并且基于具有MOS兼容结构的半导体可变电容器，其适用于集成电路，其具有至少三个端子，其中一个用于通过增加器件的另外两个端子来调制电容值或者相对于设备的主端子之一降低其直流电压。此外，本发明解耦AC信号和DC控制电压，防止RF信号的失真。本发明描述了一种可控制的电容器，其电容值不一定与其控制电压成线性关系，但是尽管其特性可能突然地被用于制造具有数字控制的半导体可变电容器，以改善其噪声和线性性能，同时保持高品质因数。

70. 发明申请

US20140367831A1 VARIABLE CAPACITANCE DEVICES 有权
标题翻译：可变电容器件
公开(公告)号：US20140367831A1
公开(公告)日：2014-12-18
申请号：US13916620
申请日：2013-06-13
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hsiao-Tsung YEN , Cheng-Wei LUO
IPC分类号： H01L29/93 , H01L29/66
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0682 , H01L28/40 , H01L29/66166 , H01L29/8605 , H01L2924/0002 , H01L2924/00
摘要： A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable resistor includes a gate structure formed over a channel region defined in a doped well formed in a semiconductor substrate. A resistance of the variable resistor is based on a voltage applied to the gate structure, which adjusts a resistance of the channel and a capacitance of the variable capacitance device.
摘要翻译：可变电容器件包括具有与电容器串联耦合的第一电容和可变电阻器的电容器。可变电阻器包括形成在形成在半导体衬底中的掺杂阱中限定的沟道区上的栅极结构。可变电阻器的电阻基于施加到栅极结构的电压，其调节通道的电阻和可变电容器件的电容。

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