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61. 发明授权

US09620243B2 Test system simultaneously testing semiconductor devices 有权
公开(公告)号：US09620243B2
公开(公告)日：2017-04-11
申请号：US14731784
申请日：2015-06-05
申请人： Sunghun Park
发明人： Sunghun Park
IPC分类号： G11C29/44 , G11C17/16 , G11C29/06 , G11C29/26
CPC分类号： G11C29/44 , G11C29/06 , G11C29/26 , G11C2029/2602
摘要： Individual memory chips are simultaneously tested by a tester using selectively enabled stress modules that apply a corresponding stress test to memory cells, wherein each stress test is associated with a corresponding failure attribute for the memory cells. Built-in self-test (BIST)/built-in self-stress (BISS) circuitry is provided in each stress module and may configured to selectively apply one or more stress test(s) during the simultaneous testing of a plurality of memory chips.

62. 发明授权

US09484086B2 Determination of word line to local source line shorts 有权
标题翻译：确定字线到本地源线短路
公开(公告)号：US09484086B2
公开(公告)日：2016-11-01
申请号：US14328027
申请日：2014-07-10
申请人： SANDISK TECHNOLOGIES LLC
发明人： Sagar Magia , Jagdish M. Sabde
IPC分类号： G11C11/56 , G11C29/00 , G11C16/04 , G11C29/02 , G11C29/06 , G11C29/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C29/025 , G11C29/06 , G11C2029/1202
摘要： A number of techniques determine defects in non-volatile memory arrays, which are particularly applicable to 3D NAND memory, such as BiCS type. Word line to word line shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used to determine word line to word line leaks between different blocks. Select gate leak line leakage, for both the word lines and other select lines, is considered, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques determine shorts between bit lines and low voltage circuitry, such as in sense amplifiers.
摘要翻译：许多技术确定非易失性存储器阵列中的缺陷，其特别适用于3D NAND存储器，例如BiCS型。通过应用AC应力模式来确定存储器块内的字线与字线短路，然后进行缺陷检测操作。可以使用块间应力和检测操作来确定不同块之间的字线到字线泄漏。对于字线和其他选择线都选择栅极泄漏线泄漏，也被认为是字线的短路，并选择线到本地源极线。除了字线和选择线缺陷之外，技术还可以确定位线和低电压电路之间的短路，例如读出放大器。

63. 发明授权

US09472269B2 Stress balancing of circuits 有权
标题翻译：电路的应力平衡
公开(公告)号：US09472269B2
公开(公告)日：2016-10-18
申请号：US14178955
申请日：2014-02-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Igor Arsovski , Nathaniel R. Chadwick , John B. Deforge , Ezra D. B. Hall , Kirk D. Peterson
IPC分类号： G11C11/419 , G11C29/06
CPC分类号： G11C11/419 , G11C29/06
摘要： Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method includes characterizing fatigue of a location in a memory array by skewing a bit line voltage of the location. The method also includes determining that the location is unbalanced based on the characterizing. Further, the method includes inverting a logic state of the location. Additionally, the method includes changing a value of an inversion indicator corresponding to the location.
摘要翻译：应力平衡场效应晶体管的方法，系统和结构受到偏置温度不稳定性引起的阈值电压偏移。一种方法包括通过偏移位置的位线电压来表征存储器阵列中的位置的疲劳。该方法还包括基于特征确定位置不平衡。此外，该方法包括反转位置的逻辑状态。此外，该方法包括改变对应于该位置的反转指示符的值。

64. 发明授权

US09449718B2 Method for setting a flash memory for HTOL testing 有权
标题翻译： HTOL测试闪存设置方法
公开(公告)号：US09449718B2
公开(公告)日：2016-09-20
申请号：US14566060
申请日：2014-12-10
申请人： Semiconductor Manufacturing International (Beijing) Corporation , Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Yipeng Chan , Kijun Kim , Guoxu Zhao , Xiao Ye , Zhen Yang
IPC分类号： G11C29/50 , G11C16/30 , G11C29/06 , G11C29/44 , G11C16/00
CPC分类号： G11C29/50004 , G11C16/00 , G11C16/30 , G11C29/06 , G11C29/44
摘要： A method for setting voltages in a flash memory for high temperature operating life (HTOL) testing is provided. The flash memory includes a substrate, a source, and a control gate. The method includes adjusting the voltages that are applied to the source, the control gate, and the substrate, such that there is no voltage difference between the control gate and the source, and no voltage difference between the control gate and the substrate. Specifically, adjusting the voltages includes setting the voltage that is applied to the source to a ground voltage, setting the voltage that is applied to the control gate to the ground voltage, and setting the voltage that is applied to the substrate to a power supply voltage.
摘要翻译：提供了一种用于设置用于高温工作寿命（HTOL）测试的闪速存储器中的电压的方法。闪存包括基板，源极和控制栅极。该方法包括调整施加到源极，控制栅极和衬底的电压，使得控制栅极和源极之间没有电压差，并且控制栅极和衬底之间没有电压差。具体地，调整电压包括将施加到源极的电压设定为接地电压，将施加到控制栅极的电压设定为接地电压，将施加到基板的电压设定为电源电压。

65. 发明授权

US09310426B2 On-going reliability monitoring of integrated circuit chips in the field 有权
标题翻译：现场集成电路芯片的可靠性监控
公开(公告)号：US09310426B2
公开(公告)日：2016-04-12
申请号：US13626040
申请日：2012-09-25
申请人： International Business Machines Corporation
发明人： Theodoros E. Anemikos , Douglas S. Dewey , Pascal A. Nsame , Anthony D. Polson
IPC分类号： G06G7/54 , G01R31/28 , G01R31/30 , G11C29/06 , G11C29/12 , G11C11/412 , G11C29/04
CPC分类号： G01R31/2856 , G01R31/2872 , G01R31/2894 , G01R31/3004 , G11C11/412 , G11C29/06 , G11C29/12005 , G11C2029/0401 , G11C2029/0409
摘要： Disclosed is an integrated circuit (IC) chip with a built-in self-test (BIST) architecture that allows for in the field accelerated stress testing. The IC chip can comprise an embedded processor, which selectively alternates operation of an on-chip test block between a stress mode and a test mode whenever the IC chip is powered-on such that, during the stress mode, the test block operates at a higher voltage level than an on-chip functional block and such that, during the test mode, the test block operates at a same voltage level as the functional block and is subjected to testing. Also disclosed are a system, method and computer program product which access the results of such testing from IC chips in a variety of different types of products in order model IC chip performance degradation and to generate IC chip end of life predictions specific to the different types of products.
摘要翻译：公开了具有内置自检（BIST）架构的集成电路（IC）芯片，允许在现场加速压力测试。 IC芯片可以包括一个嵌入式处理器，每当IC芯片通电时，它可选择地在应力模式和测试模式之间交替片上测试块的操作，使得在应力模式期间，测试块在使得在测试模式期间，测试块在与功能块相同的电压电平下工作并进行测试。还公开了一种系统，方法和计算机程序产品，其从各种不同类型的产品中的IC芯片访问这种测试的结果，以便将IC芯片的性能降级降级并产生特定于不同类型的IC芯片寿命终止预测的产品。

66. 发明授权

US09147467B2 Electronic device 有权
标题翻译：电子设备
公开(公告)号：US09147467B2
公开(公告)日：2015-09-29
申请号：US14191409
申请日：2014-02-26
申请人： SK hynix Inc.
发明人： Hoe-Gwon Jeong
IPC分类号： G11C13/00 , G11C11/56 , G11C29/06 , G11C29/50 , G11C11/16
CPC分类号： G11C29/12 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C29/06 , G11C29/50008 , G11C2029/5002 , G11C2211/5643 , G11C2211/5645
摘要： An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.
摘要翻译：一种电子设备，包括半导体存储器单元，其可以包括可变电阻元件，所述可变电阻元件被配置为响应于流过其两端的电流而改变其电阻值;触发数据生成单元，被配置为生成逻辑值切换的触发数据在用于测试可变电阻元件的可靠性的第一模式中的预定周期，被配置为传送从外部输入的数据的数据传输线以及被构造成以预定周期在其方向上改变的流动的驱动单元，通过可变电阻元件响应于第一模式中的触发数据，以及响应于数据传输线的数据确定的方向的流量通过可变电阻元件，以写入日期的第二模式或从其读取数据可变电阻元件。

67. 发明授权

US09053821B2 Semiconductor device performing stress test 有权
标题翻译：半导体器件进行压力测试
公开(公告)号：US09053821B2
公开(公告)日：2015-06-09
申请号：US14243183
申请日：2014-04-02
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
IPC分类号： G11C7/00 , G11C29/00 , G11C29/06 , G11C29/12 , G11C29/28 , G11C29/02 , G11C29/50 , G11C29/26
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.
摘要翻译：半导体器件包括存储单元阵列，其通过多个读出放大器阵列被分成多个存储单元阵列，并且多个存储单元阵列中的每一个包括多个字线和用于执行测试控制的测试电路一次激活在多个存储单元垫中彼此不邻近设置的多个所选存储单元垫中的每一个中包括的多个字线。根据本发明，分配具有多个激活字线的存储单元垫。因此，与在一个存储单元垫中激活的许多字线相比，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小。因此，可以同时激活更多的字线。

68. 发明授权

US09019787B2 Semiconductor device having hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体器件
公开(公告)号：US09019787B2
公开(公告)日：2015-04-28
申请号：US13888707
申请日：2013-05-07
申请人： PS4 Luxco S.A.R.L.
发明人： Yasuhiro Matsumoto , Noriaki Mochida , Takeshi Ohgami , Daiki Izawa
IPC分类号： G11C7/00 , G11C5/06 , G11C11/4074 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C7/18 , G11C29/00 , G11C29/06 , G11C29/12
CPC分类号： G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C29/006 , G11C29/06 , G11C2029/1204
摘要： A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.
摘要翻译：公开了一种具有分层位线的半导体器件，其包括：第一全局位线; 第一和第二局部位线共同耦合到第一全局位线; 第一和第二电力线; 耦合在第一局部位线和第一电源线之间的第一晶体管; 耦合在所述第二局部位线和所述第二电源线之间的第二晶体管; 耦合在第一和第二电力线之间的第三晶体管。

69. 发明授权

US08984353B2 Information storage device and test method of setting a test condition for information storage device outside range of presupposed real use conditions 有权
标题翻译：信息存储装置和设置信息存储装置的测试条件在预先设定的实际使用条件范围之外的试验方法
公开(公告)号：US08984353B2
公开(公告)日：2015-03-17
申请号：US13010363
申请日：2011-01-20
申请人： Kiyoshi Takeuchi
发明人： Kiyoshi Takeuchi
IPC分类号： G11C29/50 , G11C29/00 , G11C11/41 , G11C29/06 , G11C29/12
CPC分类号： G11C29/50 , G11C11/41 , G11C29/06 , G11C29/12005 , G11C2029/5004
摘要： A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately.
摘要翻译：提供一种测试具有标记的随机变化的信息存储设备的操作余量的方法，以及具有自诊断操作余量功能的信息存储设备。测试方法包括测试包括多个存储器位的信息存储设备，因为测试条件被设置为处于实际使用信息存储设备预先设定的条件的范围内，并且对存储器位数进行计数失败了。测试方法还包括基于计数值验证信息存储设备的操作余量的大小。测试条件变得严重，参考值被设置为相当大的值，以使得能够高精度地测试噪声的操作余量。

70. 发明授权

US08270239B2 Semiconductor memory device and methods of performing a stress test on the semiconductor memory device 失效
标题翻译：半导体存储器件以及对半导体存储器件进行应力测试的方法
公开(公告)号：US08270239B2
公开(公告)日：2012-09-18
申请号：US12330747
申请日：2008-12-09
申请人： Nan Chen , Changho Jung , Zhiqin Chen
发明人： Nan Chen , Changho Jung , Zhiqin Chen
IPC分类号： G11C29/50 , G11C29/06 , G11C29/00 , G11C11/41 , G11C11/413 , G11C8/08 , G11C7/12
CPC分类号： G11C29/50 , G11C11/41 , G11C29/24 , G11C2029/1204
摘要： A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode.
摘要翻译：提供一种在半导体存储器件上执行应力测试的半导体存储器件和方法。在一个示例中，半导体存储器件包括复用器装置，其被配置为在应力模式期间将控制半导体存储器件的内部定时的定时信号从内部信号切换到外部信号，并且还包括一个或多个字线在应力模式期间接收应力电压的半导体存储器件，基于外部信号的应力模式的持续时间。在另一示例中，半导体存储器件包括被配置为在应力模式期间接收应力电压的一个或多个字线，以及被配置为在应力模式期间向半导体存储器件的位线提供预充电电压的预充电电路。

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