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1. 发明授权

US08938570B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08938570B2
公开(公告)日：2015-01-20
申请号：US14330223
申请日：2014-07-14
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshiro Riho
IPC分类号： G06F3/06 , G11C7/10 , G06F13/00
CPC分类号： G11C7/10 , G11C5/02 , G11C7/20 , G11C8/12 , G11C8/18 , G11C29/023 , G11C29/028 , H01L23/481 , H01L24/06 , H01L24/14 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05082 , H01L2224/05087 , H01L2224/05096 , H01L2224/05548 , H01L2224/05567 , H01L2224/05568 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13564 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01055 , H01L2924/01074 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/14361 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device includes a controller chip, a plurality of semiconductor chips operatively connected to the controller chip, wherein at least one of the plurality of semiconductor chips is operatively supplied with a pulse signal from the controller chip, and operatively supplied identification information, wherein each of the plurality of semiconductor chips is configured to store the identification information in response to the pulse signal received from the controller chip, and wherein each of the plurality of semiconductor chips is configured to block transmission of the pulse signal to a following semiconductor chip in a signal path among the plurality of semiconductor chips until identification information is stored therein.
摘要翻译：半导体器件包括控制器芯片，可操作地连接到控制器芯片的多个半导体芯片，其中多个半导体芯片中的至少一个可操作地被提供有来自控制器芯片的脉冲信号，以及可操作地提供的识别信息，其中每个配置为响应于从控制器芯片接收的脉冲信号来存储识别信息，并且其中多个半导体芯片中的每一个被配置为阻止脉冲信号传输到随后的半导体芯片多个半导体芯片之间的信号路径，直到识别信息被存储在其中。

2. 发明授权

US09053821B2 Semiconductor device performing stress test 有权
标题翻译：半导体器件进行压力测试
公开(公告)号：US09053821B2
公开(公告)日：2015-06-09
申请号：US14243183
申请日：2014-04-02
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
IPC分类号： G11C7/00 , G11C29/00 , G11C29/06 , G11C29/12 , G11C29/28 , G11C29/02 , G11C29/50 , G11C29/26
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.
摘要翻译：半导体器件包括存储单元阵列，其通过多个读出放大器阵列被分成多个存储单元阵列，并且多个存储单元阵列中的每一个包括多个字线和用于执行测试控制的测试电路一次激活在多个存储单元垫中彼此不邻近设置的多个所选存储单元垫中的每一个中包括的多个字线。根据本发明，分配具有多个激活字线的存储单元垫。因此，与在一个存储单元垫中激活的许多字线相比，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小。因此，可以同时激活更多的字线。

3. 发明授权

US08937488B2 Calibration of impedance 有权
标题翻译：阻抗校准
公开(公告)号：US08937488B2
公开(公告)日：2015-01-20
申请号：US14266217
申请日：2014-04-30
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshiro Riho
IPC分类号： H03K17/16 , H03K19/00
CPC分类号： H03K19/0005 , H03K19/018521 , H04L25/0278
摘要： A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.
摘要翻译：半导体器件具有第一受控芯片，包括具有与第一输出电路相同的配置的第一复制输出电路，连接到第一复制输出电路的第一ZQ端子，连接到第一ZQ端子的第一通电极和第一控制电路，其设置第一复制输出电路的阻抗。控制芯片包括连接到第一贯通电极的第二ZQ端子，将第二ZQ端子的电压与参考电压进行比较的比较器电路，以及基于比较器电路进行比较的处理的第二控制电路123 。第一控制电路和第二控制电路接收公共输入信号以操作并顺序地改变和设置阻抗，直到当外部电阻元件连接到第二ZQ端子时比较结果改变。

4. 发明授权

US08988919B2 Semiconductor device having a control chip stacked with a controlled chip 有权
标题翻译：具有堆叠有受控芯片的控制芯片的半导体器件
公开(公告)号：US08988919B2
公开(公告)日：2015-03-24
申请号：US14274267
申请日：2014-05-09
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshiro Riho
IPC分类号： G11C5/06 , G11C7/22 , G11C7/10 , G11C7/06 , G11C11/4063 , H03L7/097 , G11C29/02 , G11C11/4076 , G11C11/4093 , G11C11/4096 , H03L7/081 , G11C11/40 , H01L25/065
CPC分类号： G11C11/4063 , G11C5/063 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/40 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C29/023 , G11C29/028 , H01L25/0657 , H01L2224/16145 , H01L2924/1305 , H01L2924/13091 , H03L7/0812 , H03L7/097 , H01L2924/00
摘要： A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit.
摘要翻译：半导体器件包括第一受控芯片和与其堆叠的控制芯片。第一受控芯片包括响应于同步信号输出数据信号的第一电路，与延迟同步信号同步地将数据信号输出到数据端的输入/输出电路，复制输出电路并输出与延迟的同步信号同步的第一副本终端的复制信号。控制芯片包括输出同步信号并接收数据信号的第一控制电路，延迟同步信号并将其作为延迟同步信号输出的延迟调整电路，比较复制信号和同步的相位的相位比较器电路信号，以及延迟控制电路，其基于相位比较器电路的比较结果来控制延迟调整电路的延迟量。

5. 再颁专利

USRE47840E1 Testing circuits in stacked wafers using a connected electrode in the first wafer 有权
公开(公告)号：USRE47840E1
公开(公告)日：2020-02-04
申请号：US14820325
申请日：2015-08-06
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshiro Riho
IPC分类号： G11C7/00 , G11C5/06
摘要： A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.

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