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1. 发明授权

US08000165B2 Self reset clock buffer in memory devices 有权
公开(公告)号：US08000165B2
公开(公告)日：2011-08-16
申请号：US12207011
申请日：2008-09-09
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.

2. 发明申请

US20100226191A1 Leakage Reduction in Memory Devices 有权
标题翻译：内存设备中的泄漏减少
公开(公告)号：US20100226191A1
公开(公告)日：2010-09-09
申请号：US12397142
申请日：2009-03-03
申请人： Changho Jung , Nan Chen , Cheng Zhong , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Cheng Zhong , Zhiqin Chen
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/00 , G11C7/22 , G11C8/08 , G11C11/4094 , G11C11/413 , G11C2207/2227 , H03K19/0016
摘要： A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches are added for pre-charge devices to further reduce leakage current.
摘要翻译：存储器件包括包括存储器单元的核心阵列。存储器件还包括耦合到芯阵列的头灯和正电源电压。磁头开关通过将磁芯阵列与正电源电压断开来减少来自磁芯阵列的漏电流。另外，增加头开关用于预充电器件，以进一步减少泄漏电流。

3. 发明授权

US08270239B2 Semiconductor memory device and methods of performing a stress test on the semiconductor memory device 失效
标题翻译：半导体存储器件以及对半导体存储器件进行应力测试的方法
公开(公告)号：US08270239B2
公开(公告)日：2012-09-18
申请号：US12330747
申请日：2008-12-09
申请人： Nan Chen , Changho Jung , Zhiqin Chen
发明人： Nan Chen , Changho Jung , Zhiqin Chen
IPC分类号： G11C29/50 , G11C29/06 , G11C29/00 , G11C11/41 , G11C11/413 , G11C8/08 , G11C7/12
CPC分类号： G11C29/50 , G11C11/41 , G11C29/24 , G11C2029/1204
摘要： A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode.
摘要翻译：提供一种在半导体存储器件上执行应力测试的半导体存储器件和方法。在一个示例中，半导体存储器件包括复用器装置，其被配置为在应力模式期间将控制半导体存储器件的内部定时的定时信号从内部信号切换到外部信号，并且还包括一个或多个字线在应力模式期间接收应力电压的半导体存储器件，基于外部信号的应力模式的持续时间。在另一示例中，半导体存储器件包括被配置为在应力模式期间接收应力电压的一个或多个字线，以及被配置为在应力模式期间向半导体存储器件的位线提供预充电电压的预充电电路。

4. 发明授权

US07948824B2 Self reset clock buffer in memory devices 有权
标题翻译：存储器中的自复位时钟缓冲器
公开(公告)号：US07948824B2
公开(公告)日：2011-05-24
申请号：US12792982
申请日：2010-06-03
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.
摘要翻译：存储器件包括时钟缓冲电路。时钟缓冲电路包括交叉耦合逻辑电路。交叉耦合逻辑电路具有至少两个逻辑门，其中至少一个逻辑门的输出耦合到至少一个逻辑门的输入。交叉耦合逻辑电路耦合到用于接受时钟信号的输入端。该存储器件还包括一个可从交叉耦合逻辑电路的输出产生时钟信号的时钟驱动器。从时钟信号到交叉耦合逻辑电路的反馈环路控制交叉耦合逻辑电路。包括三态反相器的缓冲电路耦合到时钟信号以保持时钟信号，同时避免与时钟发生器的争用。存储器件通过片选信号使能。

5. 发明申请

US20100061161A1 Self Reset Clock Buffer In Memory Devices 有权
公开(公告)号：US20100061161A1
公开(公告)日：2010-03-11
申请号：US12207011
申请日：2008-09-09
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C7/00 , G11C8/18 , H03K19/00 , H03K3/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.

6. 发明申请

US20100238756A1 Self Reset Clock Buffer In Memory Devices 有权
标题翻译：内存器件中的自复位时钟缓冲器
公开(公告)号：US20100238756A1
公开(公告)日：2010-09-23
申请号：US12792982
申请日：2010-06-03
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C8/18 , H03K19/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.
摘要翻译：存储器件包括时钟缓冲电路。时钟缓冲电路包括交叉耦合逻辑电路。交叉耦合逻辑电路具有至少两个逻辑门，其中至少一个逻辑门的输出耦合到至少一个逻辑门的输入。交叉耦合逻辑电路耦合到用于接受时钟信号的输入端。该存储器件还包括一个可从交叉耦合逻辑电路的输出产生时钟信号的时钟驱动器。从时钟信号到交叉耦合逻辑电路的反馈环路控制交叉耦合逻辑电路。包括三态反相器的缓冲电路耦合到时钟信号以保持时钟信号，同时避免与时钟发生器的争用。存储器件通过芯片选择信号使能。

7. 发明申请

US20100097206A1 Post Cap for Guardrail with Luminous Lamp 审中-公开
标题翻译：带有发光灯的护栏邮箱
公开(公告)号：US20100097206A1
公开(公告)日：2010-04-22
申请号：US12642335
申请日：2009-12-18
申请人： Changho Jung , Wonjeong Jeong
发明人： Changho Jung , Wonjeong Jeong
IPC分类号： G08B1/08 , F21V9/00 , G01S19/14 , E01F15/00 , G06K7/01
CPC分类号： E01F15/0461
摘要： The present invention relates to a post cap for a guardrail equipped with light emission means. The post cap for a guardrail is configured to produce beautiful scenery through variation in the color and the blinking state and to ensure safe nighttime passage through the transmission of signals depending on situations. The post cap for a guardrail equipped with light emission means capable of emitting light of various colors is configured to detect the location of installation and time through the reception of GPS signals and to enable a plurality of post caps to implement variations in color in conjunction with each other through time-based variations in color according to a stored program based on the location of installation.
摘要翻译：本发明涉及一种装有发光装置的护栏的柱盖。护栏的后盖配置为通过颜色和闪烁状态的变化产生美丽的风景，并根据情况确保安全的夜间通过信号传输。配备有能够发射各种颜色的光的发光装置的护栏的柱盖被配置为通过接收GPS信号来检测安装位置和时间，并且使得多个后盖可以结合根据基于安装位置的存储程序，通过基于时间的颜色变化来实现。

8. 发明申请

US20130223176A1 MEMORY PRE-DECODER CIRCUITS EMPLOYING PULSE LATCH(ES) FOR REDUCING MEMORY ACCESS TIMES, AND RELATED SYSTEMS AND METHODS 有权
标题翻译：使用脉冲锁存器（ES）减少存储器访问时间的内存预解码器电路及相关系统和方法
公开(公告)号：US20130223176A1
公开(公告)日：2013-08-29
申请号：US13463873
申请日：2012-05-04
申请人： Esin Terzioglu , Changho Jung , Shahzad Nazar
发明人： Esin Terzioglu , Changho Jung , Shahzad Nazar
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a pre-decoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path.
摘要翻译：公开了采用用于减少存储器访问时间的脉冲锁存器的存储器预解码器电路以及相关的系统和方法。在一个实施例中，存储器预解码器电路包括存储器预解码器，其被配置为对在存储器预解码设置路径内输入的存储器地址进行预解码，以产生预解码的存储器地址输入。此外，在存储器预解码设置路径外部的存储器预解码器电路中提供脉冲锁存器。脉冲锁存器基于时钟信号对预解码的存储器地址输入进行采样，并产生预解码的存储器地址输出。因此，存储器预译码设置路径在脉冲锁存器的时钟信号之前建立预先解码的存储器地址输入。以这种方式，脉冲锁存器被配置为产生预解码的存储器地址输出，而不增加存储器预解码设置路径中的建立时间。

9. 发明授权

US08811109B2 Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods 有权
标题翻译：使用脉冲锁存器来减少存储器访问时间的存储器预解码器电路，以及相关的系统和方法
公开(公告)号：US08811109B2
公开(公告)日：2014-08-19
申请号：US13463873
申请日：2012-05-04
申请人： Esin Terzioglu , Changho Jung , Shahzad Nazar
发明人： Esin Terzioglu , Changho Jung , Shahzad Nazar
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a pre-decoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path.
摘要翻译：公开了采用用于减少存储器访问时间的脉冲锁存器的存储器预解码器电路以及相关的系统和方法。在一个实施例中，存储器预解码器电路包括存储器预解码器，其被配置为对在存储器预解码设置路径内输入的存储器地址进行预解码以生成预解码的存储器地址输入。此外，在存储器预解码设置路径外部的存储器预解码器电路中提供脉冲锁存器。脉冲锁存器基于时钟信号对预解码的存储器地址输入进行采样，并产生预解码的存储器地址输出。因此，存储器预译码设置路径在脉冲锁存器的时钟信号之前建立预先解码的存储器地址输入。以这种方式，脉冲锁存器被配置为产生预解码的存储器地址输出，而不增加存储器预解码设置路径中的建立时间。

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