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61. 发明申请

US20080217049A1 EMBEDDED CAPACITIVE STACK 有权
公开(公告)号：US20080217049A1
公开(公告)日：2008-09-11
申请号：US12045660
申请日：2008-03-10
申请人： George Dudnikov
发明人： George Dudnikov
IPC分类号： H05K1/16
CPC分类号： H05K1/162 , H01G4/06 , H01G4/30 , H01G4/306 , H05K1/0216 , H05K1/0231 , H05K1/113 , H05K1/18 , H05K3/4602 , H05K3/4641 , H05K2201/0191 , H05K2201/0209 , H05K2201/0257 , H05K2201/0355 , H05K2201/093 , H05K2201/09309 , H05K2201/09518 , H05K2201/09663 , H05K2203/162 , Y10T29/43 , Y10T29/435 , Y10T29/49036 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155
摘要： A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

62. 发明申请

US20080214136A1 Reduction of near field electro-magnetic scattering using high impedance metallization terminations 有权
公开(公告)号：US20080214136A1
公开(公告)日：2008-09-04
申请号：US12121828
申请日：2008-05-16
申请人： Gerard James Hayes , Scott Ladell Vance
发明人： Gerard James Hayes , Scott Ladell Vance
IPC分类号： H04B1/10
CPC分类号： H05K9/0039 , H04B1/3838 , H05K1/0216 , H05K1/0224 , H05K1/0231 , H05K1/0233 , H05K1/0234 , H05K1/167 , H05K2201/093 , H05K2201/09354 , H05K2201/10022 , H05K2201/1003 , H05K2201/10446
摘要： The present invention uses metallization termination techniques to reduce the electro-magnetic field scattering at the edges of metallized areas. The metallization termination techniques provide a gradual transition from high conductivity areas to high impedance areas. The mobile phone antenna illuminates the PCB allowing currents to flow on the PCB. When the currents reach edges of the PCB they flow through a region of increasingly high impedance without reflecting back or scattering.

63. 发明授权

US07361994B2 System to control signal line capacitance 有权
标题翻译：系统控制信号线电容
公开(公告)号：US07361994B2
公开(公告)日：2008-04-22
申请号：US11239952
申请日：2005-09-30
申请人： Xiaoning Ye
发明人： Xiaoning Ye
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/49827 , H01L23/49816 , H01L23/49838 , H01L23/645 , H01L2224/16 , H01L2924/01078 , H01L2924/15311 , H05K1/0251 , H05K1/116 , H05K3/429 , H05K2201/093 , H05K2201/0969 , H05K2201/09718 , H05K2201/09727
摘要： A system may include a conductive plane defining a non-conductive antipad area and a second non-conductive area extending from the antipad area in at least a first direction, a dielectric plane coupled to the conductive plane, a conductive via passing through the dielectric plane and the antipad area, a conductive pad connected to an end of the conductive via, and a conductive trace coupled to the dielectric plane and connected to the conductive pad, the conductive trace extending from the conductive pad in the first direction.
摘要翻译：系统可以包括限定非导电止动区域的导电平面和在至少第一方向上从止血区域延伸的第二非导电区域，耦合到导电平面的电介质平面，穿过电介质平面的导电通孔并且所述反面区域，连接到所述导电通孔的端部的导电焊盘以及耦合到所述电介质平面并连接到所述导电焊盘的导电迹线，所述导电迹线从所述导电焊盘沿所述第一方向延伸。

64. 发明授权

US07361843B2 AC coupling of power plane sections using improved capacitance stitching material 有权
标题翻译：使用改进的电容缝合材料进行交流耦合
公开(公告)号：US07361843B2
公开(公告)日：2008-04-22
申请号：US11236960
申请日：2005-09-28
申请人： Ernest Lentschke , Jeffrey C. Hailey , Raymond McCormick
发明人： Ernest Lentschke , Jeffrey C. Hailey , Raymond McCormick
IPC分类号： H05K1/03
CPC分类号： H05K1/0231 , H05K1/0227 , H05K1/162 , H05K2201/0209 , H05K2201/093 , H05K2201/09663 , H05K2201/09881 , Y10T29/4913
摘要： An information handling system has a printed circuit board with a split power plane having a plurality of sections that may be used for distributing different voltages on a single conductive foil layer of the printed circuit board to components on the printed circuit board. Capacitive coupling of the split power plane sections may be enhanced with a high dielectric fill between the portions.
摘要翻译：信息处理系统具有印刷电路板，其具有分割电源平面，具有多个部分，该多个部分可用于将印刷电路板的单个导电箔层上的不同电压分配到印刷电路板上的组件。分开的功率平面部分的电容耦合可以通过部分之间的高电介质填充来增强。

65. 发明申请

US20080059919A1 COMPUTER PROGRAM FOR BALANCING POWER PLANE PIN CURRENTS IN A PRINTED WIRING BOARD 有权
标题翻译：印刷电路板平衡电源引脚电流的计算机程序
公开(公告)号：US20080059919A1
公开(公告)日：2008-03-06
申请号：US11936673
申请日：2007-11-07
申请人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
发明人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
IPC分类号： G06F17/50
CPC分类号： H05K1/0265 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2201/10189 , Y10T29/49156
摘要： A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.
摘要翻译：用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

66. 发明授权

US07324348B2 Telecommunications chassis and card 有权
标题翻译：电信机箱和卡
公开(公告)号：US07324348B2
公开(公告)日：2008-01-29
申请号：US11171081
申请日：2005-06-28
申请人： Robin Berg, Jr. , Todd Husom , Derek Sayres
发明人： Robin Berg, Jr. , Todd Husom , Derek Sayres
IPC分类号： H05K5/00
CPC分类号： H04Q1/10 , H04Q1/023 , H04Q1/03 , H04Q1/035 , H04Q1/116 , H04Q2201/06 , H04Q2201/10 , H04Q2201/12 , H05K1/0216 , H05K1/14 , H05K1/18 , H05K7/1425 , H05K7/186 , H05K2201/044 , H05K2201/093 , H05K2201/09354 , H05K2201/09663
摘要： A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.
摘要翻译：公开了一种底盘和相关通信电路卡。底盘具有散热和阻燃特征，同时容纳高密度的电路卡。实施例包括具有双层中间层的内壳，其将底盘分成顶部和底部室。每个层具有部分对准的槽，并且在两层之间提供气隙。实施例还包括在两个网格层之间具有气隙的双层网状覆盖物。在内壳体的内表面上设置突起和凹槽，以接收在一个边缘上具有引导件的电路卡和另一边缘上的翅片。电路卡包括导体结构，例如具有配对和分离的导体的多个板层。电路卡还包括定位成与底盘的通风特征配合的一些组件，并且包括一些选择用于低功耗或降低可燃性的组件。

67. 发明申请

US20070289771A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070289771A1
公开(公告)日：2007-12-20
申请号：US11755045
申请日：2007-05-30
申请人： HIDEKI OSAKA , YUTAKA UEMATSU , EIICHI SUZUKI
发明人： HIDEKI OSAKA , YUTAKA UEMATSU , EIICHI SUZUKI
IPC分类号： H05K1/00
CPC分类号： H05K1/0236 , H01L23/66 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0231 , H05K1/0237 , H05K1/141 , H05K2201/093 , H05K2201/09309 , H05K2201/09663 , H05K2201/09681 , H05K2201/09727 , H05K2201/09972 , H05K2201/10734 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention realizes high density mounting along with achieving power source sharing by a digital semiconductor element and an analog semiconductor element in a semiconductor device. An power layer for analog is connected to one end of an EBG layer, a power layer for digital is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog and the EBG layer from each other is disposed between the power layer for analog and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of power source to an analog chip.
摘要翻译：本发明通过数字半导体元件和半导体器件中的模拟半导体元件实现电源共享，实现了高密度安装。用于模拟的功率层连接到EBG层的一端，用于数字的功率层连接到EBG层的另一端，各个元件的接地端子连接到公共接地层，接地层用于将模拟功率层和EBG层彼此分离设置在用于模拟的功率层和EBG层之间。因此，实现了高密度安装，同时降低了电源对模拟芯片的干扰。

68. 发明授权

US07304858B2 Printed circuit board unit and electronic apparatus 有权
标题翻译：印刷电路板单元和电子设备
公开(公告)号：US07304858B2
公开(公告)日：2007-12-04
申请号：US11023489
申请日：2004-12-29
申请人： Akiyoshi Saitou
发明人： Akiyoshi Saitou
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： H05K1/0233 , H05K1/0215 , H05K1/0224 , H05K1/18 , H05K3/429 , H05K2201/093 , H05K2201/09309 , H05K2201/0969 , H05K2201/1003 , H05K2201/1006 , H05K2201/10189 , H05K2201/10409
摘要： A printed circuit board has separate first, second and third sections arranged in a predetermined direction. A connector is mounted at the first section. A noise cut filter is mounted at the second section and connected to the connector. An electronic circuit component is mounted at the third section and connected to the noise cut filter. An electrically conductive power source layer is formed within the printed circuit board at a position outside a peripheral section adjacent the second section. The noise cut filter is allowed to operate without receiving any influence of noise from the power source layer. Noise is sufficiently removed at the noise cut filter. Noise is suppressed to the utmost in electric signals in the connector. Radiation of noise is reliably reduced at the connector. Electromagnetic interference can be suppressed.
摘要翻译：印刷电路板具有沿预定方向布置的单独的第一，第二和第三部分。连接器安装在第一部分。噪声截止滤波器安装在第二部分并连接到连接器。电子电路部件安装在第三部分并连接到噪声截止滤波器。在印刷电路板的与第二部分相邻的周边部分外的位置处形成导电电源层。允许噪声抑制滤波器工作，而不会受到来自电源层的噪声的任何影响。噪声在噪音截止滤波器上被充分去除。连接器中的电信号最大限度地抑制噪声。连接器可靠地降低噪声辐射。可以抑制电磁干扰。

69. 发明授权

US07282647B2 Apparatus for improving coupling across plane discontinuities on circuit boards 有权
标题翻译：用于改善电路板上平面不连续性的耦合的装置
公开(公告)号：US07282647B2
公开(公告)日：2007-10-16
申请号：US10329188
申请日：2002-12-23
申请人： Weston Roth , Jayne L. Mershon , Xang Moua , Jason A. Mix
发明人： Weston Roth , Jayne L. Mershon , Xang Moua , Jason A. Mix
IPC分类号： H05K1/03
CPC分类号： H05K1/0234 , H05K1/0225 , H05K1/0227 , H05K1/023 , H05K1/167 , H05K2201/0195 , H05K2201/0323 , H05K2201/093 , H05K2201/09309 , H05K2201/09663 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49163 , Y10T29/49165
摘要： The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.
摘要翻译：本发明涉及一种用于改善电路板上的平面不连续性的耦合的装置和方法。电路板包括形成在电压参考平面上的不连续性，例如分裂，槽或切口。导电层覆盖不连续点。导电层具有连接到下面的参考平面的第一部分和跨越不连续部分的第二部分。第一部分使用插槽或通孔连接到参考平面。并且导电层具有在参考平面上延伸但保持与其断开的第三部分。导电层可以是石墨或炭黑。

70. 发明授权

US07276668B2 Circuit board with mounting pads for reducing parasitic effect 有权
标题翻译：电路板带安装垫，用于减少寄生效应
公开(公告)号：US07276668B2
公开(公告)日：2007-10-02
申请号：US10964619
申请日：2004-10-15
申请人： Sheng-Yuan Lee , Ya-Chi Liao
发明人： Sheng-Yuan Lee , Ya-Chi Liao
IPC分类号： H05K1/03
CPC分类号： H05K1/025 , H05K1/0224 , H05K1/0231 , H05K1/111 , H05K1/181 , H05K2201/0792 , H05K2201/093 , H05K2201/0969 , H05K2201/10636 , Y02P70/611
摘要： A circuit board with mounting pads is described for improving the frequency response of routing traces. The present invention is used to etch an etching hole on ground layer corresponding to the surface-mounted devices (SMD) on a routing layer and therefore the parasitic effect from the stray capacitor is reduced, resulting in eliminating the parasitic effect in high-frequency and raising the quality of the PCB as well.
摘要翻译：描述了具有安装焊盘的电路板，用于改善路由迹线的频率响应。本发明用于蚀刻对应于路由层上的表面安装器件（SMD）的接地层上的蚀刻孔，因此来自杂散电容器的寄生效应降低，从而消除了高频下的寄生效应，提高PCB的质量。

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