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61. 发明授权

US08762608B1 System on a chip serial communication interface method and apparatus 失效
标题翻译：系统芯片串行通讯接口方法及装置
公开(公告)号：US08762608B1
公开(公告)日：2014-06-24
申请号：US14072620
申请日：2013-11-05
申请人： Marvell International Ltd.
发明人： Roger Longstreet , Vivek Raghunath Khanzode , Hongying Sheng
IPC分类号： G06F13/12
CPC分类号： G01R31/3177 , G06F11/267 , G06F11/273 , G06F13/1684 , G06F13/385 , G06F13/4282 , H03M9/00
摘要： A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.
摘要翻译：本文描述了用于测试芯片上的系统块（SOC）的系统，装置和方法。根据各种实施例的SOC可以包括串行通信接口，其被配置为通过片外串行通信接口将来自SOC的选定块的信号流复用，串行化和/或并行化到片外测试单元。可以描述和要求保护其他实施例。

62. 发明授权

US08760328B1 Interface circuitry for an integrated circuit system 有权
标题翻译：集成电路系统的接口电路
公开(公告)号：US08760328B1
公开(公告)日：2014-06-24
申请号：US13620126
申请日：2012-09-14
申请人： Wei Yee Koay , Chin Ghee Ch'ng , Ket Chiew Sia , Tony Ngai , Sean Woei Voon
发明人： Wei Yee Koay , Chin Ghee Ch'ng , Ket Chiew Sia , Tony Ngai , Sean Woei Voon
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： An integrated circuit system may include a first integrated circuit (IC), a second IC, and interface circuitry. The first IC is operable to output a parallel data stream at a first data rate. The second IC is operable to output a serialized data stream at a second date rate. The second data rate may be different than the first data rate. The interface circuitry may be coupled between the first integrated circuit and the second integrated circuit. The interface circuitry may be operable to convert the parallel data stream received from the first IC into a serialized data stream with the second data rate. The interface circuitry may be also operable to convert the serialized data stream received from the second IC to a parallel data stream with the first data rate.
摘要翻译：集成电路系统可以包括第一集成电路（IC），第二IC和接口电路。第一IC可操作以以第一数据速率输出并行数据流。第二IC可操作地以第二日期速率输出串行数据流。第二数据速率可能不同于第一数据速率。接口电路可以耦合在第一集成电路和第二集成电路之间。接口电路可以用于将从第一IC接收的并行数据流转换成具有第二数据速率的串行数据流。接口电路还可以用于将从第二IC接收的串行数据流转换成具有第一数据速率的并行数据流。

63. 发明申请

US20140159780A1 DATA INTERFACE CLOCK GENERATION 有权
标题翻译：数据接口时钟产生
公开(公告)号：US20140159780A1
公开(公告)日：2014-06-12
申请号：US14181969
申请日：2014-02-17
申请人： Wei-Lien Yang
发明人： Wei-Lien Yang
IPC分类号： H03K3/017 , H03L7/08
CPC分类号： H03K3/017 , H03K23/68 , H03L7/08 , H03L7/0891 , H03M9/00 , H04L1/0003 , H04L7/033
摘要： In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.
摘要翻译：在一个实施例中，装置可以包括时钟发生器以产生第一时钟信号。该装置还可以包括基于传输时钟信号和并行输入数据产生串行数据的串行器。该装置还可以包括基于第一时钟信号和串行数据产生至少两个差分信号的信号发生器。

64. 发明授权

US08743642B2 Data serializers, output buffers, memory devices and methods of serializing 有权
标题翻译：数据串行器，输出缓冲器，存储器件和序列化方法
公开(公告)号：US08743642B2
公开(公告)日：2014-06-03
申请号：US13491311
申请日：2012-06-07
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1048 , G11C7/1057 , G11C7/1072 , G11C11/4093 , G11C2207/107 , H03M9/00
摘要： Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage.
摘要翻译：提供了数据串行器，输出缓冲器，存储器件和用于串行化的方法，包括可将并行数据的数字转换为串行数据数字的对应数字流的数据串行器。一个这样的数据串行器可以包括接收并行数据位的逻辑系统和具有彼此相位分开的相位的时钟信号。这样的数据串行器可以使用时钟信号来产生具有对应于并行数据位中的相应一个的值的值的数据采样信号和对应于相应的一个时钟信号的定时。数据采样信号可以被施加到包括在输出节点和第一电压之间并联耦合的多个开关（诸如相应的晶体管）的开关电路。

65. 发明授权

US08692699B2 Data interface clock generation 失效
标题翻译：数据接口时钟生成
公开(公告)号：US08692699B2
公开(公告)日：2014-04-08
申请号：US13545275
申请日：2012-07-10
申请人： Wei-Lien Yang
发明人： Wei-Lien Yang
IPC分类号： H03M9/00
CPC分类号： H03K3/017 , H03K23/68 , H03L7/08 , H03L7/0891 , H03M9/00 , H04L1/0003 , H04L7/033
摘要： In one embodiment, an apparatus may include a clock generator to generate a format clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the format clock signal and the serial data.
摘要翻译：在一个实施例中，设备可以包括时钟发生器以产生格式时钟信号。该装置还可以包括基于传输时钟信号和并行输入数据产生串行数据的串行器。该装置还可以包括基于格式时钟信号和串行数据产生至少两个差分信号的信号发生器。

66. 发明申请

US20140043179A1 METHOD AND APPARATUS FOR DIRECT DIGITAL SYNTHESIS OF SIGNALS USING TAYLOR SERIES EXPANSION 有权
标题翻译：使用TAYLOR系列扩展的信号的直接数字合成的方法和装置
公开(公告)号：US20140043179A1
公开(公告)日：2014-02-13
申请号：US14054370
申请日：2013-10-15
申请人： M.S. RAMAIAH SCHOOL OF ADVANCED STUDIES
发明人： Dipayan MAZUMDAR , Govind Rangaswamy KADAMBI
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , G06F1/0356 , H03M9/00
摘要： A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series of a sinusoid function.
摘要翻译：提供了使用泰勒级数展开的信号的直接数字合成（DDS）方法和装置。 DDS可以包括修改的相位到幅度转换器，其包括只读存储器（ROM），寄存器以及对应于相应更高分辨率相位角的单个尺寸，例如粗略，中间和精细ROM。当组合时，ROM的输出可以形成正弦函数的泰勒级数形式的数字输出信号。

67. 发明授权

US08643516B1 Parallel-to-serial converter 有权
标题翻译：并行到串行转换器
公开(公告)号：US08643516B1
公开(公告)日：2014-02-04
申请号：US13669137
申请日：2012-11-05
申请人： Venkata N. S. N. Rao
发明人： Venkata N. S. N. Rao
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A method for converting parallel data having a certain word size to serial data, comprises the steps of: loading a first segment of a word of the parallel data into a shift register having a first size, and inputting remaining segments of the word into two or more multiplexers connected in series for selecting a next segment of the word; selecting the next segment of the word to load into the shift register; shifting out the loaded segment of the word in the shift register as serial data output; loading the selected next segment of the word into the shift register; and repeating the selecting, shifting, and loading the next segment steps until all the remaining segments of the word have been shifted as serial data output.
摘要翻译：一种用于将具有特定字大小的并行数据转换为串行数据的方法包括以下步骤：将并行数据的字的第一段加载到具有第一大小的移位寄存器中，并将该字的剩余段输入到两个或更多的多路复用器串联连接，用于选择单词的下一段; 选择字的下一段加载到移位寄存器中; 将移位寄存器中的字的加载段移出串行数据输出; 将所选择的下一个段加载到移位寄存器中; 并重复选择，移动和加载下一段步骤，直到该单词的所有剩余段已经被移位为串行数据输出。

68. 发明授权

US08619762B2 Low power deserializer and demultiplexing method 失效
标题翻译：低功率解串器和解复用方法
公开(公告)号：US08619762B2
公开(公告)日：2013-12-31
申请号：US12147326
申请日：2008-06-26
申请人： ChulKyu Lee , George Alan Wiley
发明人： ChulKyu Lee , George Alan Wiley
IPC分类号： H04L12/50 , H04Q11/04
CPC分类号： H04Q11/04 , H03M9/00
摘要： A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit streams. The first and second bit streams are respectively serially shifted along a first plurality of shift registers and a second plurality of shift registers. A first portion of the first bit stream in the first plurality of shift registers is selected and a second portion of the second bit stream in the second plurality of shift registers is also selected. A parallel group of data in a parallel data stream is formed from the first and second portions.
摘要翻译：解串器电路和方法根据并行分组将串行比特流转换成并行比特流。解串器和方法包括将串行数据流交替解复用为第一和第二位流。第一和第二比特流分别沿着第一多个移位寄存器和第二多个移位寄存器串行移位。选择第一多个移位寄存器中的第一比特流的第一部分，并且还选择第二多个移位寄存器中的第二比特流的第二部分。并行数据流中的并行数据组由第一和第二部分形成。

69. 发明授权

US08611379B2 Resonant clock amplifier with a digitally tunable delay 有权
标题翻译：具有数字可调延迟的谐振时钟放大器
公开(公告)号：US08611379B2
公开(公告)日：2013-12-17
申请号：US13094484
申请日：2011-04-26
申请人： Bharath Raghavan , Jun Cao , Afshin Momtaz
发明人： Bharath Raghavan , Jun Cao , Afshin Momtaz
IPC分类号： H04J3/04
CPC分类号： H03K5/07 , H03K2005/00071 , H03K2005/00208 , H03M9/00 , H04L7/0079 , H04L7/02 , H04L7/027 , H04L7/033
摘要： A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.
摘要翻译：可编程频率接收机包括用于以第一频率接收数据的分片器，用于以第二频率解复用数据的解复用器，用于产生第一频率的时钟的可编程时钟发生器，以及第一和第二谐振时钟放大器用于在第一和第二频率处放大时钟信号。谐振时钟放大器包括具有低Q值的电感器，允许它们在接收器的可编程频率范围上放大时钟信号。第二谐振时钟放大器包括数字可调谐延迟元件，以在限幅器和解复用器之间的接口处在数据窗口中延迟和居中放大的第二频率的时钟信号。延迟元件可以是电容器。校准电路调整主时钟发生器内的电容元件，以产生第一个频率的主时钟。

70. 发明授权

US08570203B2 Method and apparatus for direct digital synthesis of signals using Taylor series expansion 有权
标题翻译：使用泰勒级数扩展直接数字合成信号的方法和装置
公开(公告)号：US08570203B2
公开(公告)日：2013-10-29
申请号：US13389562
申请日：2010-10-19
申请人： Dipayan Mazumdar , Govind Rangaswamy Kadambi
发明人： Dipayan Mazumdar , Govind Rangaswamy Kadambi
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , G06F1/0356 , H03M9/00
摘要： A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single adder. Values stored in the ROMs may produce one component of a sinusoid signal, and each of the ROMs may be of a different size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series expansion of a sinusoid function.
摘要翻译：提供了使用泰勒级数展开的信号的直接数字合成（DDS）方法和装置。 DDS可以包括修改的相位到幅度转换器，其包括只读存储器（ROM），寄存器和单个加法器。存储在ROM中的值可以产生正弦信号的一个分量，并且每个ROM可以具有不同的大小，例如对应于相应较高分辨率相位角的粗略，中间和精细ROM。当组合时，ROM的输出可以以正弦函数的泰勒级数展开的形式形成数字输出信号。

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