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61. 发明授权

US08384458B1 Phase interpolation circuit 有权
标题翻译：相位插补电路
公开(公告)号：US08384458B1
公开(公告)日：2013-02-26
申请号：US13330615
申请日：2011-12-19
申请人： Chen-Wei Huang
发明人： Chen-Wei Huang
IPC分类号： H03K3/017
CPC分类号： H03K5/131 , H03K5/1565 , H03K2005/00052
摘要： A phase interpolation circuit including a first multiplexer, a second multiplexer, an interpolator and a duty-cycle repeater is provided. The first multiplexer receives a plurality of even order signals. The second multiplexer receives a plurality of odd order signals. The interpolator receives a first reference signal composed of one of the even order signals through the first multiplexer, and receives a second reference signal composed of one of the odd order signals through the second multiplexer. The interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal. The duty-cycle repeater adjusts the duty cycle of the differential input signal and accordingly generates a differential output signal with 50% duty cycle.
摘要翻译：提供了包括第一多路复用器，第二多路复用器，内插器和占空比中继器的相位插值电路。第一多路复用器接收多个偶数阶信号。第二多路复用器接收多个奇数阶信号。内插器通过第一多路复用器接收由偶数阶信号中的一个组成的第一参考信号，并通过第二多路复用器接收由奇数阶信号之一构成的第二参考信号。内插器根据数字控制信号将第一参考信号和第二参考信号之间的相位差分成多个子相位，并选择一个子相以产生差分输入信号。占空比中继器调节差分输入信号的占空比，因此产生占空比为50％的差分输出信号。

62. 发明申请

US20130002344A1 ANALOG DELAY LINES AND ADAPTIVE BIASING 有权
公开(公告)号：US20130002344A1
公开(公告)日：2013-01-03
申请号：US13612454
申请日：2012-09-12
申请人： Feng Lin
发明人： Feng Lin
IPC分类号： G05F1/10
CPC分类号： H03K5/133 , H03H11/26 , H03H11/265 , H03K5/131
摘要： Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.

63. 发明申请

US20120313683A1 PROGRAMMABLE DELAY GENERATOR AND CASCADED INTERPOLATOR 有权
标题翻译：可编程延时发生器和嵌入式插槽
公开(公告)号：US20120313683A1
公开(公告)日：2012-12-13
申请号：US13158079
申请日：2011-06-10
申请人： SERGEY V. RYLOV
发明人： SERGEY V. RYLOV
IPC分类号： H03K5/13 , H03H11/16 , H03H11/26
CPC分类号： H03K5/131 , H03H11/265 , H03K2005/00065
摘要： A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line.
摘要翻译：提供可编程延迟发生器和级联插值器。可编程延迟发生器包括第一延迟线和第二延迟线，每个具有相同数量的相应多个级。第一行的每一级包括相应的延迟缓冲器，并具有一个信号输入和一个信号输出。第二行的每一级包括相应的选择元件，并且具有两个信号输入，一个选择输入用于选择两个信号输入之一和一个信号输出。第一行和第二行并行配置，互连，并具有相同的信号传播方向。由第二行的每一级提供的每个延迟步骤等于通过第一行的一级的延迟与通过第二行的一级的延迟之间的差。

64. 发明申请

US20120306552A1 APPARATUS AND SYSTEM OF IMPLEMENTATION OF DIGITAL PHASE INTERPOLATOR WITH IMPROVED LINEARITY 有权
标题翻译：具有改进线性的数字相位插值器的实现装置和系统
公开(公告)号：US20120306552A1
公开(公告)日：2012-12-06
申请号：US13153190
申请日：2011-06-03
申请人： Mustafa Ulvi Erdogan
发明人： Mustafa Ulvi Erdogan
IPC分类号： H03L7/06 , H03K17/687
CPC分类号： H03K5/133 , H03K5/131 , H03K2005/00052 , H03L7/0812 , H03L7/16
摘要： An apparatus comprising: a first control switch driven by a first bit value; a first weighted switch driven by a first clock signal; a first intermediate node coupled between the first control switch and the second weighted switch; a first precharge transistor coupled to the first intermediate node, wherein the precharge transistor is driven by an inverse of the clock signal; a second control switch driven by an inverse of the bit; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; a second precharge transistor coupled to the second intermediate node, wherein the second precharge transistor is driven by an inverse of the second clock signal; and a capacitor coupled to the first control switch, the second control switch, the first precharge transistor and the second precharge transistor.
摘要翻译：一种装置，包括：由第一位值驱动的第一控制开关; 由第一时钟信号驱动的第一加权开关; 耦合在所述第一控制开关和所述第二加权开关之间的第一中间节点; 耦合到所述第一中间节点的第一预充电晶体管，其中所述预充电晶体管由所述时钟信号的反相驱动; 由位的反相驱动的第二控制开关; 由第二时钟信号驱动的第二加权开关; 耦合在第二控制开关和第二加权开关之间的第二中间节点; 耦合到第二中间节点的第二预充电晶体管，其中第二预充电晶体管由第二时钟信号的反相驱动; 以及耦合到第一控制开关，第二控制开关，第一预充电晶体管和第二预充电晶体管的电容器。

65. 发明授权

US08278986B2 Trimming of a pseudo-closed loop programmable delay line 有权
标题翻译：微调闭环可编程延迟线
公开(公告)号：US08278986B2
公开(公告)日：2012-10-02
申请号：US12977093
申请日：2010-12-23
申请人： Luca Bettini , Guido De Sandre
发明人： Luca Bettini , Guido De Sandre
IPC分类号： H03L7/00
CPC分类号： H03K5/131 , H03K5/133 , H03K2005/00071 , H03K2005/00084 , H03K2005/00104 , H03K2005/00123 , H03K2005/00143 , H03L7/0814
摘要： An embodiment is proposed for trimming a programmable delay line in an integrated device, which delay line is adapted to delay an input signal being synchronous with a synchronization signal of the integrated device—by a total delay. An embodiment of a corresponding method includes the steps of: preliminary programming the delay line to provide a selected nominal value of the total delay equal to a period of the timing signal, and trimming the delay line to vary an actual value of the total delay until the actual value of the total delay matches the period of the synchronization signal.
摘要翻译：提出了一种用于修整集成器件中的可编程延迟线的实施例，该延迟线适于延迟与集成器件的同步信号同步的输入信号 - 总延迟。相应方法的实施例包括以下步骤：对延迟线进行初步编程以提供等于定时信号的周期的总延迟的选定标称值，以及修整延迟线以改变总延迟的实际值，直到总延迟的实际值与同步信号的周期匹配。

66. 发明授权

US08253463B1 Pulse width control circuitry 有权
标题翻译：脉宽控制电路
公开(公告)号：US08253463B1
公开(公告)日：2012-08-28
申请号：US12721488
申请日：2010-03-10
申请人： Jeffrey Christopher Chromczak , David Lewis
发明人： Jeffrey Christopher Chromczak , David Lewis
IPC分类号： H03K5/04
CPC分类号： H03K3/017 , H03K3/0375 , H03K5/131
摘要： Integrated circuits with pulse latches are provided. Pulse latches are controlled by clock pulse signals. The clock pulse signals are generated by pulse generators. The pulse generators are controlled by adaptive pulse width control circuitry to provide clock pulse signals with a minimum pulse width and with sufficient margin to tolerate for process, voltage, and temperature variations. The pulse width control circuitry may include a replica pulse generator, a test data generation circuit, a test latch, and a pulse width calibration circuit. The replica pulse generator controls the test latch. The test latch may attempt to latch the test data. The pulse width control circuit may determine if the test latch properly latches the test data with the given pulse width. The pulse width control circuit adjusts the pulse generator dynamically to provide a minimized pulse width.
摘要翻译：提供具有脉冲锁存器的集成电路。脉冲锁存器由时钟脉冲信号控制。时钟脉冲信号由脉冲发生器产生。脉冲发生器由自适应脉冲宽度控制电路控制，以提供具有最小脉冲宽度的时钟脉冲信号，并具有足够的裕度以容忍过程，电压和温度变化。脉冲宽度控制电路可以包括复制脉冲发生器，测试数据产生电路，测试锁存器和脉冲宽度校准电路。复制脉冲发生器控制测试锁存器。测试锁存器可以尝试锁存测试数据。脉冲宽度控制电路可以确定测试锁存器是否以给定的脉冲宽度适当地锁存测试数据。脉冲宽度控制电路动态地调节脉冲发生器以提供最小的脉冲宽度。

67. 发明授权

US08248136B1 Low-power, glitch-less, configurable delay element 有权
标题翻译：低功耗，无毛刺，可配置延迟元件
公开(公告)号：US08248136B1
公开(公告)日：2012-08-21
申请号：US13007804
申请日：2011-01-17
申请人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
发明人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
摘要翻译：在一个实施例中，可配置延迟元件具有三个阶段。第一级具有8缓冲器第一延迟链和（8×1）第一多路复用器，其选择八个第一延迟链输出之一。第二级具有连接的24缓冲器第二延迟链，用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的（4×1）第二复用器。第三级具有96缓冲器第三延迟链，用于接收第二多路复用器输出，并组织成三个32缓冲子链和（4×1）第三复用器，选择四个第三延迟链输出中的一个作为延迟元件输出信号。延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。控制器基于延迟元件输出信号的更新时序。

68. 发明申请

US20120044003A1 SKEW ADJUSTMENT CIRCUIT AND SKEW ADJUSTMENT METHOD 有权
标题翻译： SKEW调整电路和SKEW调整方法
公开(公告)号：US20120044003A1
公开(公告)日：2012-02-23
申请号：US13179326
申请日：2011-07-08
申请人： Atsushi ITOU , Susumu KOJIMA
发明人： Atsushi ITOU , Susumu KOJIMA
IPC分类号： H03L7/18
CPC分类号： H03L7/0816 , H03K5/131 , H03L7/0805 , H04L25/14
摘要： A skew adjustment circuit, provided in an integrated circuit device having a plurality of signal lines transmitting a plurality of signals respectively, and a plurality of buffer circuits to which a plurality of signals transmitted through the signal lines are respectively input, has: a plurality of delay circuits, respectively provided in stages preceding the buffer circuits; a monitoring circuit monitoring changes in the signals of the plurality of signal lines; and a delay adjustment circuit, which decides delay amounts for the plurality of delay circuits based on a monitoring result output of the monitoring circuit, and sets the delay amounts in the plurality of delay circuits. The monitoring circuit detects, as the monitoring result, a number of signal changes in the signal lines in which a signal change occurs in a monitoring period, and the delay adjustment circuit decides the delay amounts based on the number of signal changes.
摘要翻译：一种偏置调整电路，具有分别输入多个信号的多个信号线的集成电路装置和分别通过信号线发送的多个信号的多个缓冲电路，具有：多个延迟电路，分别设置在缓冲电路之前的阶段; 监视电路监视多条信号线的信号的变化; 以及延迟调整电路，其基于监视电路的监视结果输出来决定多个延迟电路的延迟量，并设定多个延迟电路中的延迟量。作为监视结果，监视电路检测在监视期间发生信号变化的信号线中的多个信号变化，延迟调整电路根据信号变化次数来决定延迟量。

69. 发明授权

US08120409B2 Programmable delay circuit with integer and fractional time resolution 有权
$Programmable delay circuit with integer and fractional time resolution$
标题翻译：具有整数和分数时间分辨率的可编程延迟电路
公开(公告)号：US08120409B2
公开(公告)日：2012-02-21
申请号：US11962045
申请日：2007-12-20
申请人： Mustafa Keskin , Marzio Pedrali-Noy
发明人： Mustafa Keskin , Marzio Pedrali-Noy
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path.
摘要翻译：描述了能够提供整数和分数时间分辨率的延迟的可编程延迟电路。在一个示例性设计中，装置包括第一和第二延迟电路。第一延迟电路提供整数个时间单位的第一延迟。第二延迟电路耦合到第一延迟电路并且提供一个时间单位的一小部分的第二延迟。第一延迟电路可以包括串联耦合的多个单位延迟单元。每个单元延迟单元可以在启用时提供一个时间单位的延迟。第二延迟电路可以具有第一和第二路径。当选择时，第一路径可以提供更短的延迟，并且第二路径可以在选择时提供更长的延迟。第二路径可以耦合到至少一个虚拟逻辑门，其提供额外的负载以获得用于第二路径的更长的延迟。

70. 发明申请

US20110001537A1 DELAY LINE 失效
标题翻译：延迟线
公开(公告)号：US20110001537A1
公开(公告)日：2011-01-06
申请号：US12627415
申请日：2009-11-30
申请人： Kyung-Hoon KIM
发明人： Kyung-Hoon KIM
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： A delay line includes a delay amount adjusting unit configured to adjust a delay amount of an input signal in response to a first delay control code, and a delay unit configured to determine a number of first delay blocks having a delay amount with a first variation width and a number of second delay blocks having a delay amount with a second variation width in response to a second delay control code, wherein the delay amount with the first variation width and the delay amount with the second variation width are determined by the delay amount adjusting unit and the first and second variation widths correspond to a level change of a power supply.
摘要翻译：延迟线包括延迟量调整单元，被配置为响应于第一延迟控制代码来调整输入信号的延迟量;以及延迟单元，被配置为确定具有第一变化宽度的延迟量的第一延迟块的数量以及响应于第二延迟控制代码具有第二变化宽度的延迟量的多个第二延迟块，其中具有第一变化宽度的延迟量和具有第二变化宽度的延迟量由延迟量调整确定单元，并且第一和第二变化宽度对应于电源的电平变化。

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