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    • 4. 发明授权
    • Low-power configurable delay element
    • 低功耗可配置延迟元件
    • US08461894B1
    • 2013-06-11
    • US13585142
    • 2012-08-14
    • Fulong ZhangZheng ChenChien Kuang ChenJohn Schadt
    • Fulong ZhangZheng ChenChien Kuang ChenJohn Schadt
    • H03H11/26
    • H03K5/131
    • In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
    • 在一个实施例中,可配置延迟元件具有三个阶段。 第一级具有8缓冲器第一延迟链和(8×1)第一多路复用器,其选择八个第一延迟链输出之一。 第二级具有连接的24缓冲器第二延迟链,用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的(4×1)第二复用器 。 第三级具有96缓冲器第三延迟链,用于接收第二多路复用器输出,并组织成三个32缓冲子链和(4×1)第三复用器,选择四个第三延迟链输出中的一个 作为延迟元件输出信号。 延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。 控制器基于延迟元件输出信号的更新时序。
    • 5. 发明授权
    • Low-power, glitch-less, configurable delay element
    • 低功耗,无毛刺,可配置延迟元件
    • US08248136B1
    • 2012-08-21
    • US13007804
    • 2011-01-17
    • Fulong ZhangZheng ChenChien Kuang ChenJohn Schadt
    • Fulong ZhangZheng ChenChien Kuang ChenJohn Schadt
    • H03H11/26
    • H03K5/131
    • In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
    • 在一个实施例中,可配置延迟元件具有三个阶段。 第一级具有8缓冲器第一延迟链和(8×1)第一多路复用器,其选择八个第一延迟链输出之一。 第二级具有连接的24缓冲器第二延迟链,用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的(4×1)第二复用器 。 第三级具有96缓冲器第三延迟链,用于接收第二多路复用器输出,并组织成三个32缓冲子链和(4×1)第三复用器,选择四个第三延迟链输出中的一个 作为延迟元件输出信号。 延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。 控制器基于延迟元件输出信号的更新时序。