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61. 发明授权

US07652513B2 Slave latch controlled retention flop with lower leakage and higher performance 有权
标题翻译：从锁存控制保持触发器具有较低的泄漏和更高的性能
公开(公告)号：US07652513B2
公开(公告)日：2010-01-26
申请号：US11895853
申请日：2007-08-27
申请人： Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
发明人： Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
IPC分类号： H03K3/356
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/356147
摘要： In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.
摘要翻译：在用于数据保持的方法和装置中，第一锁存器锁存数据输入端，耦合到第一锁存器的第二锁存器保持数据输入，而第一锁存器在备用电源模式下不起作用。第二锁存器包括具有逆变器输入和反相器输出的第二锁存逆变器。可以实现为三态逆变器的开关电路耦合到逆变器输出端，逆变器输入端和保持信号。切换电路可在待机功率模式下操作，以响应于保持信号断言反相器输入处的逻辑状态。逻辑状态与备用电源模式中保留的数据输入相一致。备用电源可操作以将待机功率模式的电力提供给第二锁存逆变器，开关电路和保持输入。

62. 发明申请

US20070079149A1 Programmable I/O cell capable of holding its state in power-down mode 有权
标题翻译：可编程I / O单元能够在掉电模式下保持其状态
公开(公告)号：US20070079149A1
公开(公告)日：2007-04-05
申请号：US11241277
申请日：2005-09-30
申请人： Biranchinath Sahu , Douglas Pastorello , Golam Chowdhury
发明人： Biranchinath Sahu , Douglas Pastorello , Golam Chowdhury
IPC分类号： G06F1/26
CPC分类号： H03K3/0375 , H03K3/356147 , H03K19/0008
摘要： The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
摘要翻译：本发明包括一个微控制器单元，其包括用于产生掉电信号的处理器。控制逻辑响应于掉电信号产生保持信号。电压调节器响应于输入电压提供调节电压，并响应于掉电信号而断电。响应于稳压器进入断电状态，由调节电压供电的至少一个数字设备进入断电模式。所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。输入/输出单元也被连接以接收保持信号。当至少一个数字设备进入掉电状态时，输入/输出单元响应于保持信号维持数字输出信号的最后状态。

63. 发明申请

US20070075760A1 SOURCE DRIVE CIRCUIT 有权
标题翻译：源驱动电路
公开(公告)号：US20070075760A1
公开(公告)日：2007-04-05
申请号：US11469214
申请日：2006-08-31
申请人： CHING-WU TSENG , Alex Tang
发明人： CHING-WU TSENG , Alex Tang
IPC分类号： H03K3/00
CPC分类号： G09G3/3688 , G02F1/13306 , G09G2310/0289 , H03K3/356147
摘要： A latchable voltage level shifter is provided. The latchable voltage level shifter comprises: a voltage level shifter receiving an original input signal and generating a high voltage signal according to a timing sequence of a first phase control signal; and a high voltage flip-flop, coupled to the voltage level shifter, receiving the high voltage signal and a second phase control signal, the high voltage flip-flop latching the high voltage signal according to a timing sequence of the second phase control signal and outputting a high voltage output signal. The latchable voltage level shifter can be used in a source drive circuit so as to reduce the layout area and production cost.
摘要翻译：提供可锁定电压电平转换器。可锁定电压电平移位器包括：电压电平移位器，接收原始输入信号，并根据第一相位控制信号的定时序列产生高电压信号; 以及耦合到电压电平移位器的高电压触发器，接收高电压信号和第二相位控制信号，高电平触发器根据第二相位控制信号的定时序列来锁存高电压信号;以及输出高压输出信号。可锁定电压电平转换器可用于源驱动电路，以减少布局面积和生产成本。

64. 发明授权

US07068088B2 Soft-error rate improvement in a latch 失效
标题翻译：锁存器中的软错误率提高
公开(公告)号：US07068088B2
公开(公告)日：2006-06-27
申请号：US10976034
申请日：2004-10-27
申请人： John T. Petersen
发明人： John T. Petersen
IPC分类号： H03K3/356
CPC分类号： H03K3/0375 , H03K3/356147
摘要： In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. The input of a first inverter is connected to the output of a second inverter. The input of a second inverter is connected to the output of the first inverter. When the input to the first inverter is disturbed by a soft error event, a signal tristates the first inverter.
摘要翻译：在优选实施例中，本发明提供了用于减少锁存器中的软错误事件的电路和方法。第一反相器的输入连接到第二反相器的输出端。第二反相器的输入连接到第一反相器的输出端。当第一反相器的输入被软错误事件干扰时，信号使第一个反相器变为三态。

65. 发明授权

US07028069B1 Dynamic circuit using exclusive states 失效
标题翻译：动态电路采用独占状态
公开(公告)号：US07028069B1
公开(公告)日：2006-04-11
申请号：US09996865
申请日：2001-11-27
申请人： Edward T. Pak , Sivakumar Doraiswamy
发明人： Edward T. Pak , Sivakumar Doraiswamy
IPC分类号： G06F7/50
CPC分类号： H03K3/356147
摘要： The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of the adders by cutting the latch delay while not requiring complex clocking.
摘要翻译：本发明提供了一种在噪声条件下稳健的动态多米诺骨牌电路。本发明还提供了一种动态加法器，其包含可以在不损害面积或速度的情况下产生真实动态反演的节点。本发明通过在不需要复杂时钟的情况下切断锁存延迟来进一步提高加法器的速度。

66. 发明授权

US06980194B2 Amplitude conversion circuit for converting signal amplitude 有权
标题翻译：用于转换信号幅度的幅度转换电路
公开(公告)号：US06980194B2
公开(公告)日：2005-12-27
申请号：US10376241
申请日：2003-03-03
申请人： Youichi Tobita
发明人： Youichi Tobita
IPC分类号： G09G3/36 , H03K3/356 , H03K19/0175 , H03K19/0185 , H03L5/00
CPC分类号： H03K3/356113 , G09G3/3648 , G09G2310/0289 , H03K3/356147 , H03K19/018507
摘要： A level shifter includes first and second P-type TFTs for latching a level of first and second output nodes, first and second N-type TFTs for setting the level of the first and second output nodes, and a drive circuit. The drive circuit includes third to eighth N-type TFTs providing, in response to rising and falling edges of an input signal, a voltage higher than a threshold voltage of the first and second N-type TFTs, between the gate and source of the first and second N-type TFTs, and includes first and second capacitors and a resistor element. Accordingly, even if an amplitude voltage of an input signal is smaller than the threshold voltage of the first and second N-type TFTs, the level shifter operates normally.
摘要翻译：电平移位器包括用于锁存第一和第二输出节点电平的第一和第二P型TFT，用于设定第一和第二输出节点电平的第一和第二N型TFT以及驱动电路。驱动电路包括第三至第八N型TFT，响应于输入信号的上升沿和下降沿，在第一和第二N型TFT的栅极和源极之间提供高于第一和第二N型TFT的阈值电压的电压和第二N型TFT，并且包括第一和第二电容器和电阻器元件。因此，即使输入信号的振幅电压小于第一和第二N型TFT的阈值电压，电平转换器也正常工作。

67. 发明申请

US20050184784A1 Flip-flops, shift registers, and active-matrix display devices 有权
标题翻译：触发器，移位寄存器和有源矩阵显示设备
公开(公告)号：US20050184784A1
公开(公告)日：2005-08-25
申请号：US11043178
申请日：2005-01-27
申请人： Hajime Washio , Yuhichiroh Murakami , Michael Brownlow
发明人： Hajime Washio , Yuhichiroh Murakami , Michael Brownlow
IPC分类号： G02F1/133 , G09G3/20 , G09G3/30 , G09G3/36 , G11C11/412 , G11C19/00 , H03K3/012 , H03K3/037 , H03K3/356 , H03K23/00 , H03K3/289
CPC分类号： H03K3/356165 , G09G3/3677 , G09G3/3688 , G11C19/00 , H03K3/012 , H03K3/356113 , H03K3/356147
摘要： A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.
摘要翻译：锁存部分包括锁存电路。锁存电路包括反相器并锁存来自门控部分的输入信号。在锁存电路的一个反相器和输出端子OUT之间设置有根据复位信号的高/低切换开/关特性的模拟开关。在输出端子和用于接收作为触发器的电源的低电位的输入端之间设置有根据复位信号的高/低切换开/关特性的开关元件。

68. 发明申请

US20050077945A1 Low power, up full swing voltage CMOS bus receiver 有权
标题翻译：低功耗，全高电压CMOS总线接收器
公开(公告)号：US20050077945A1
公开(公告)日：2005-04-14
申请号：US10860522
申请日：2004-06-03
申请人： Nathalie Messina , Yves Leduc
发明人： Nathalie Messina , Yves Leduc
IPC分类号： G06F13/40 , H03B1/00 , H03K3/356 , H03L5/00
CPC分类号： H03K3/356147 , G06F13/4072 , H03K3/356113 , Y02D10/14 , Y02D10/151
摘要： A CMOS bus receiver for converting a reduced voltage swing input signal at an input node to a higher voltage swing output signal at an output node. The receiver includes a first and a second MOS transistor connected in series by their source and drain between a first side and a second side of a power supply, a gate of the first MOS transistor being connected to the input node, the common connection node of the first and second MOS transistors being connected to the output node. A third and a fourth MOS transistor connected in series by their source and drain between the first side of the power supply and the input node are also provided, a gate of the third MOS transistor being connected to the output node, and a gate of the second MOS transistor being connected to the common connection node of the third and fourth MOS transistors. A fifth MOS transistor is provided, connected in series by a source and drain with a diode between the first side of the power supply and the input node, a gate of the fourth MOS transistor being connected to the common connection node of the fifth MOS transistor and the diode. An inverter has an input connected to the output node and an output connected to a gate of the fifth MOS transistor.
摘要翻译：一种CMOS总线接收器，用于将输入节点处的降低的电压摆幅输入信号转换为输出节点处的较高电压摆幅输出信号。接收器包括通过其源极和漏极在电源的第一侧和第二侧串联连接的第一和第二MOS晶体管，第一MOS晶体管的栅极连接到输入节点，公共连接节点第一和第二MOS晶体管连接到输出节点。还提供了通过其电源的第一侧和输入节点之间的源极和漏极串联连接的第三和第四MOS晶体管，第三MOS晶体管的栅极连接到输出节点，并且栅极第二MOS晶体管连接到第三和第四MOS晶体管的公共连接节点。提供第五MOS晶体管，其通过源极和漏极串联连接在电源的第一侧和输入节点之间的二极管，第四MOS晶体管的栅极连接到第五MOS晶体管的公共连接节点和二极管。逆变器具有连接到输出节点的输入端和连接到第五MOS晶体管的栅极的输出端。

69. 发明申请

US20040246024A1 Voltage level converter device 失效
标题翻译：电压电平转换器
公开(公告)号：US20040246024A1
公开(公告)日：2004-12-09
申请号：US10834382
申请日：2004-04-29
发明人： Rudiger Brede , Helmut Schneider
IPC分类号： H03K019/086
CPC分类号： H03K3/356147 , H03K3/356113
摘要： A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.
摘要翻译：一种用于将处于第一电压电平的输入信号转换成与第一电压电平不同的第二电压电平的输出信号的电压电平转换器装置，其中电压电平转换器装置至少具有一个晶体管，并且其中由控制信号控制的附加晶体管在与输入信号的电压电平相对应的电压电平处被提供在当输出信号切换以切换时相应地接通或关断的电流路径中那个路径开或关

70. 发明申请

US20030234427A1 Semiconductor device configured to allow well potential control in accordance with operation mode 审中-公开
标题翻译：半导体器件被配置为根据操作模式允许阱电位控制
公开(公告)号：US20030234427A1
公开(公告)日：2003-12-25
申请号：US10321545
申请日：2002-12-18
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Takashi Kono
IPC分类号： H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119
CPC分类号： H01L27/0921 , H01L27/0928 , H03K3/356113 , H03K3/356147
摘要： A charge transfer portion is provided, which is capable of electrically connecting, in response to a mode transition, an N well to a P well where a transistor constituting a CMOS logic circuit is formed. The charge transfer portion feeds excess charges in the N well to the P well in the mode transition, in which it is necessary to lower a potential in the N well and to raise a potential in the P well. Therefore, the mode transition can quickly be achieved without wasting the charges.
摘要翻译：提供电荷转移部分，其能够响应于模式转换将N阱电连接到形成CMOS逻辑电路的晶体管的P阱。电荷转移部分在模式转换中将N阱中的过量电荷输送给P阱，其中有必要降低N阱中的电位并提高P阱中的电位。因此，可以在不浪费费用的情况下快速实现模式转换。

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