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61. 发明授权

US5805173A System and method for capturing and transferring selected portions of a video stream in a computer system 失效
标题翻译：用于在计算机系统中捕获和传送视频流的选定部分的系统和方法
公开(公告)号：US5805173A
公开(公告)日：1998-09-08
申请号：US537491
申请日：1995-10-02
申请人： Stephen G. Glennon , Daniel P. Mulligan , Paul B. Wood
发明人： Stephen G. Glennon , Daniel P. Mulligan , Paul B. Wood
IPC分类号： G06T1/00 , H04N5/44 , H04N21/41
CPC分类号： H04N21/4113 , G06T1/0007 , H04N21/443 , H04N5/4401
摘要： Aspects of the present invention provide a system for selectively processing a video signal in accordance with instructions from application software. The system contains a video decoder for converting an analog video signal to digital video data, and a controller for formatting and routing the digital video data. A list of control structures may be loaded into a memory associated with the controller. The control structures contain formatting and routing information used by the controller to process different portions of the video stream. The number and content of control structures as well as the correlation between the control structures and selected portions of the video stream may be flexibly determined by application software. In particular, the control structures may be configured such that certain portions of the video stream are routed to the CPU for processing, while other portions are routed to a display driver and output on a display device.
摘要翻译：本发明的方面提供一种用于根据来自应用软件的指令选择性地处理视频信号的系统。该系统包括用于将模拟视频信号转换为数字视频数据的视频解码器，以及用于格式化和路由数字视频数据的控制器。可以将控制结构的列表加载到与控制器相关联的存储器中。控制结构包含由控制器用于处理视频流的不同部分的格式化和路由信息。控制结构的数量和内容以及控制结构和视频流的选定部分之间的相关性可以由应用软件灵活地确定。特别地，控制结构可以被配置为使得视频流的某些部分被路由到CPU进行处理，而其他部分被路由到显示驱动器并在显示设备上输出。

62. 发明授权

US5781132A Error correcting decoder 失效
标题翻译：错误纠正解码器
公开(公告)号：US5781132A
公开(公告)日：1998-07-14
申请号：US587755
申请日：1996-01-17
申请人： Lanny L. Lewyn
发明人： Lanny L. Lewyn
IPC分类号： H03M1/08 , H03M1/36
CPC分类号： H03M1/0809 , H03M1/365
摘要： The magnitudes of an input voltage and individual ones of progressive fractions of a reference voltage are compared to produce first and second output voltages. Each of the elements in a first logical network receives the first output voltage from an individual one of the comparators and the second output voltage from a comparator non-consecutive with (preferably 2 comparators removed from) such individual comparator. Signals from these elements pass to latches. The latches have assertion and negation outputs which pass to elements in a second logical network. When an individual one of the elements in the second logical network provides a particular output, it prevents the elements receiving outputs from comparators responsive to lower reference voltage fractions from providing the particular output. When an element in the second logical network responsive to a latch with a higher reference voltage fraction provides an output within a preset time, its output supersedes that of the lower individual element and prevents all lower elements in such logical network from responding. In this way, only the element in the second logical network responsive to the highest reference voltage fraction within the preset time provides an output after the latches are rendered non-transparent by a second clocking signal. Elements in the second logical network are strobed by a third clocking signal at a later preset time to indicate the input voltage magnitude.
摘要翻译：将参考电压的输入电压和逐行分数的个数进行比较以产生第一和第二输出电压。第一逻辑网络中的每个元件从比较器中的单独一个接收第一输出电压，并从不同于这样的单独比较器的（优选地从两个比较器中去除）的比较器不连续地接收第二输出电压。来自这些元素的信号传递到锁存器。锁存器具有传递给第二逻辑网络中的元件的断言和否定输出。当第二逻辑网络中的单个元件中的单个元件提供特定输出时，其防止从比较器接收输出的元件响应于较低参考电压分数而提供特定输出。当响应于具有较高参考电压分数的锁存器的第二逻辑网络中的元件在预设时间内提供输出时，其输出取代较低单个元件的输出，并且防止这种逻辑网络中的所有较低元件响应。以这种方式，仅在第二逻辑网络中响应于预设时间内的最高参考电压分数的元件在锁存器被第二时钟信号变得不透明之后提供输出。第二逻辑网络中的元件在稍后的预设时间被第三时钟信号选通以指示输入电压幅度。

63. 发明授权

US5717904A Apparatus and methods for automatically controlling block writes 失效
标题翻译：自动控制块写入的装置和方法
公开(公告)号：US5717904A
公开(公告)日：1998-02-10
申请号：US543236
申请日：1995-10-13
申请人： Steven B. Ehlers , Michael D. Asal
发明人： Steven B. Ehlers , Michael D. Asal
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A system for processing a stream of data and automatically selecting a portion or all of the data stream for block writing to a memory. The memory is capable of storing data in response to a block write command and a normal write command. The system contains a first data register and a second data register having the same data width. The first data register accepts data from the data stream in accordance with the its data width. Data stored in the first data register is transferred to the second data register. The first data register is then loaded with a portion of the data stream which is contiguous to the data stored in the first data register prior to the transferring. The data in the first and the second data registers is then compared. If the data in the first and the second registers is the same, then the content of a data counter is increased by one. When the content of the data counter exceeds a predetermined value, the system executes a block write command.
摘要翻译：一种用于处理数据流并自动选择用于块写入存储器的数据流的一部分或全部的系统。存储器能够响应于块写入命令和正常写入命令来存储数据。该系统包含具有相同数据宽度的第一数据寄存器和第二数据寄存器。第一数据寄存器根据其数据宽度从数据流接受数据。存储在第一数据寄存器中的数据被传送到第二数据寄存器。然后，在转移之前，第一数据寄存器被加载有与存储在第一数据寄存器中的数据相邻的数据流的一部分。然后比较第一和第二数据寄存器中的数据。如果第一和第二寄存器中的数据相同，则将数据计数器的内容增加1。当数据计数器的内容超过预定值时，系统执行块写命令。

64. 发明授权

US5640332A Multimedia graphics system 失效
标题翻译：多媒体图形系统
公开(公告)号：US5640332A
公开(公告)日：1997-06-17
申请号：US648542
申请日：1996-05-16
申请人： David C. Baker , Jonathan I. Siann
发明人： David C. Baker , Jonathan I. Siann
IPC分类号： G06F12/00 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/377 , G09G5/39 , G09G5/395 , H04N1/00 , H04N5/44 , H04N9/00 , H04N21/236 , H04N21/2365 , H04N21/2368 , H04N21/434 , G11B27/031 , H04N5/00
CPC分类号： G09G5/395 , G09G5/00 , G09G5/06 , G09G5/363 , H04N21/42653 , G09G2340/125 , G09G2352/00 , H04N5/44
摘要： Words of different types of digital information, including standard interframe video (SIF), graphics, television and audio are transferred preferably in packets between a controller, storage memory and shift registers (e.g. FIFO's) individually associated with the different information types. For a VRAM memory, information is transferred in parallel, controlled by tag bus information, from the controller to the memory and then serially to the FIFO's, all at a frequency higher than a clock frequency in a monitor raster scan. The tag bus information is decoded and introduced to an additional FIFO. A state machine processes such additional FIFO information and transfers the digital information to the different FIFO's at times controlled in each line by such additional FIFO--e.g. particular times in each line for the SIF and graphics and, thereafter, for television and audio, at times unrelated to any times in such line. The graphics transfer is timed to substantially fill, but not overflow, in such line the limited capacity of the associated FIFO. Their limited capacities cause the television and audio FIFO's to stop receiving words when filled to particular limits. For a DRAM memory, parallel information is transferred, dependent upon the tag bus information, between the controller, memory and FIFO's at the clock frequency. In a "Rambus" system, a bus common with the controller, memory and FIFO's provides control and timing words. Such words control information transfer in successive words through the common bus to the controller, memory and FIFO's upon such timing and control.
摘要翻译：不同类型的数字信息（包括标准帧间视频（SIF），图形，电视和音频）的字优选地以分组方式传送到控制器，存储存储器和与不同信息类型单独关联的移位寄存器（例如，FIFO）之间。对于VRAM存储器，信息由标签总线信息并行传输，从控制器传输到存储器，然后以监视器光栅扫描中的时钟频率高于FIFO的速度。标签总线信息被解码并被引入附加FIFO。状态机处理这样的附加FIFO信息，并通过这样的附加FIFO将数字信息传送到在每一行控制的时间的不同FIFO。 SIF和图形的每一行的特定时间，以及之后的电视和音频，有时在任何时候都不相关。图形传输的定时是基本上填充而不是溢出，在这样一行中相关联的FIFO的容量有限。它们有限的容量会导致电视和音频FIFO在满足特定限制时停止接收字词。对于DRAM存储器，根据标签总线信息，以时钟频率在控制器，存储器和FIFO之间传送并行信息。在“Rambus”系统中，与控制器，存储器和FIFO共用的总线提供控制和定时字。这样的字在这样的定时和控制下通过公共总线连续地控制信息传输到控制器，存储器和FIFO。

65. 发明授权

US5542041A Apparatus for, and methods of, providing a universal format of pixels and for scaling fields in the pixels 失效
标题翻译：用于提供像素的通用格式并用于缩放像素中的场的装置和方法
公开(公告)号：US5542041A
公开(公告)日：1996-07-30
申请号：US319427
申请日：1994-10-06
申请人： James J. Corona
发明人： James J. Corona
IPC分类号： G09G5/36 , G06T3/40 , G09G5/395 , H04N1/407 , G06F15/00
CPC分类号： G09G5/395
摘要： Raster display memories are often arranged to output groups of pixels in progressive blocks, each having a plurality of pixels and each pixel having a plurality of fields. The fields in each pixel may provide color, overlay and cursor information for an individual position on a video screen. The numbers of bits in each pixel and in each field may be variable in different applications. In this system, control information indicates the starting position of each block, the location of each pixel in each block and each field in each pixel and the width of each pixel and each field in number of bits. Using this control information, the system recovers the pixels in each block and the fields in each pixel and processes such information to provide a display of the pixel information on a video screen. The number of bits contained in each field may be expanded to a width (e.g. 8) when the field width is less than eight (8) bits. In this expansion, the expanded field value has an error, compared to the field value before expansion, less than half of the least significant bit in the expanded field. Frequently, the bits in each field before expansion are provided in the positions of greatest binary significance in the expanded field. The unused positions in the expanded field are then filled in the order of progressively decreasing significance by the bits of progressively decreasing significance in the field before expansion, starting from the bit of greatest significance.
摘要翻译：栅格显示存储器经常被布置为输出渐进块中的像素组，每个像素具有多个像素，每个像素具有多个场。每个像素中的字段可以为视频屏幕上的单个位置提供颜色，覆盖和光标信息。每个像素和每个场中的位数可以在不同的应用中变化。在该系统中，控制信息指示每个块的开始位置，每个块中的每个像素的位置和每个像素中的每个场以及每个像素的宽度和每个场的位数。使用该控制信息，系统恢复每个块中的像素和每个像素中的场，并处理这些信息以在视频屏幕上提供像素信息的显示。当字段宽度小于八（8）位时，每个字段中包含的位数可以扩展到宽度（例如8）。在这种扩展中，扩展的字段值与扩展前的字段值相比具有小于扩展字段中最低有效位的一半的错误。通常，扩展前的每个字段中的位被提供在扩展字段中具有最大二进制含义的位置。然后，从最大意义的位开始，在扩展字段中的未使用位置以逐渐减小的显着性的顺序被填充，这些比特在扩展之前的字段中逐渐减小的显着性。

66. 发明授权

US5479042A Micromachined relay and method of forming the relay 失效
标题翻译：微加工继电器和形成继电器的方法
公开(公告)号：US5479042A
公开(公告)日：1995-12-26
申请号：US12055
申请日：1903-02-01
申请人： Christopher D. James , Henry S. Katzenstein
发明人： Christopher D. James , Henry S. Katzenstein
IPC分类号： H01L29/84 , H01H1/20 , H01H59/00 , H01L29/66 , H01L29/96
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2059/0018 , Y10T307/878
摘要： A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned. The first contact is normally separated from the second contacts because the bumps engage the insulating substrate surface. When a voltage is applied between an electrically conductive layer on the insulating substrate surface and the polysilicon layer, the bridging member is deflected so that the first contact engages the second contacts. Electrical leads extend on the surface of the insulating substrate from the second contacts to bonding pads disposed adjacent a second cavity in the semiconductor substrate. The resultant relays on a wafer may be separated by sawing the semiconductor and insulating substrates at the position of the second cavity in each relay to expose the pads for electrical connections.
摘要翻译：延伸穿过半导体衬底（例如单晶硅）中的空腔的桥接构件具有连续的层 - 掩模层，导电层（例如多晶硅）和绝缘层（例如SiO 2）。第一电接触件（例如镀有钌的金）在垂直于桥接构件的延伸方向的绝缘层上延伸穿过空腔。一对凸起（例如金）在绝缘层上分别位于接触件和一个空腔端部之间。最初，桥接构件，然后在衬底上形成接触和凸块，然后通过桥接构件中的孔在衬底中蚀刻空腔。一对第二电触点（例如镀有钌的金）位于与半导体衬底相邻的绝缘衬底（例如耐热玻璃）的表面上。触点清洁后，两个基板接合。第一触点通常与第二触点分离，因为凸块与绝缘基板表面接合。当在绝缘衬底表面上的导电层和多晶硅层之间施加电压时，桥接构件被偏转，使得第一触点接合第二触点。电引线在绝缘基板的表面上从第二触点延伸到邻近半导体衬底中的第二腔的接合焊盘。可以通过在每个继电器中的第二腔的位置处锯切半导体和绝缘基板来分离晶片上的所得继电器，以露出用于电连接的焊盘。

67. 发明授权

US5406306A System for, and method of displaying information from a graphics memory and a video memory on a display monitor 失效
标题翻译：用于在显示监视器上从图形存储器和视频存储器显示信息的系统和方法
公开(公告)号：US5406306A
公开(公告)日：1995-04-11
申请号：US14359
申请日：1993-02-05
申请人： Jonathan I. Siann , Conrad M. Coffey , Jeffrey L. Easley
发明人： Jonathan I. Siann , Conrad M. Coffey , Jeffrey L. Easley
IPC分类号： G06F3/14 , G06F3/048 , G06F3/153 , G09G5/00 , G09G5/02 , G09G5/14 , G09G5/395 , H04N5/272 , G09G1/14
CPC分类号： H04N5/272 , G09G5/02 , G09G5/395 , G09G2340/12 , G09G2340/125
摘要： A display memory respectively stores, in first and second portions, digital graphics data for display in a video monitor and digital video data for display in a window in the monitor. The digital video data is transferred from the display memory to a shift register at a rate different from the pixel clock and from the shift register at a clock rate that may be lower than the pixel clock rate. The video data may be stored in a luminance and chrominance format and may be converted by a color space converter to 3 bytes representing the primary colors red, green and blue. The video pixels may then be interpolated to expand the number of video pixels. The shift register operation may be synchronized with such expansion so that data is not passed from the shift register until the expansion of previous data from the shift register has been completed. Video window logic provides for the passage of the graphics pixels through a digital multiplexer at the graphics clock rate at the monitor positions outside the window and the video pixels from the shift register through the colorspace converter and the interpolator at the monitor positions within the window. The graphics data may be delayed by a delay corresponding to that of the color space converter and the interpolator. The digital data passing through the multiplexer are latched at the graphics clock rate and are then converted to analog signals for display as a color image on the video monitor.
摘要翻译：显示存储器分别在第一和第二部分存储用于在视频监视器中显示的数字图形数据和用于在监视器中的窗口中显示的数字视频数据。数字视频数据以与像素时钟速率不同的时钟速率从像素时钟和移位寄存器以不同于时钟速率的速率从显示存储器传送到移位寄存器。视频数据可以以亮度和色度格式存储，并且可以由颜色空间转换器转换成表示原色红，绿和蓝的3字节。然后可以内插视频像素以扩大视频像素的数量。移位寄存器操作可以与这种扩展同步，使得数据不会从移位寄存器传递，直到来自移位寄存器的先前数据的扩展已经完成。视频窗口逻辑提供图形像素通过数字多路复用器，其以窗口外的监视器位置处的图形时钟速率和来自移位寄存器的视频像素通过颜色空间转换器和窗口内的监视器位置处的内插器通过。图形数据可以被延迟与颜色空间转换器和内插器的延迟相对应的延迟。通过多路复用器的数字数据以图形时钟速率锁存，然后转换为模拟信号，以便在视频监视器上显示为彩色图像。

68. 发明授权

US5406285A Digital-to-analog converter 失效
标题翻译：数模转换器
公开(公告)号：US5406285A
公开(公告)日：1995-04-11
申请号：US23359
申请日：1993-02-26
申请人： Jan C. Diffenderfer , Joseph H. Colles
发明人： Jan C. Diffenderfer , Joseph H. Colles
IPC分类号： H03M1/68 , H03M1/74 , H03M1/80
CPC分类号： H03M1/685 , H03M1/745 , H03M1/747
摘要： A system on an integrated circuit chip for providing a digital-to-analog conversion includes a plurality of output members each providing a particular current when energized. These members may be disposed on the chip in a pair of spaced columns. First control lines in the space between the columns of output members provide a thermometer code. Second control lines in this space provide a binary code. The first and second control lines are preferably parallel to the columns. When a first one of the first control lines is energized, different ones or combinations of the second control lines provide progressive values in the output members between "0" and "15", assuming four (4) of the second control lines. Similarly, when a second one of the first control lines is additionally energized, different ones or combinations of the second control lines provide progressive values between "16" and "31" in associated output members. At the same time, the output members providing a value of "15" continue to be energized. Similarly, the energizing of successive ones of the first control lines provides for the generation of analog values within progressive ranges. The output members associated with each of the first control lines are interspersed in the columns in accordance with the analog values represented by these output members to provide a first centroidal arrangement. The output members associated with each of the first control lines are also interspersed with the output members associated with the others of the first control lines to provide a second centroidal arrangement.
摘要翻译：用于提供数模转换的集成电路芯片上的系统包括多个输出构件，每个输出构件在通电时提供特定电流。这些构件可以以一对间隔的列布置在芯片上。输出构件列之间的空间中的第一个控制线提供温度计代码。该空间中的第二条控制线提供二进制代码。第一和第二控制线优选地平行于列。当第一控制线中的第一控制线被通电时，假设四（4）个第二控制线，不同的或第二控制线的组合在“0”和“15”之间的输出部件中提供逐行值。类似地，当第二控制线中的第二控制线另外通电时，不同的第一控制线或第二控制线的组合在相关联的输出部件中的“16”和“31”之间提供渐进值。同时，提供值“15”的输出成员继续通电。类似地，连续的第一控制线的通电提供在渐进范围内产生模拟值。根据由这些输出构件表示的模拟值，将与每个第一控制线相关联的输出构件分散在列中以提供第一重心布置。与第一控制线中的每一个相关联的输出部件也与与第一控制线中的其它控制线相关联的输出部件分散以提供第二重心配置。

69. 发明授权

US5406219A Differential-to-single-ended converter 失效
标题翻译：差分到单端转换器
公开(公告)号：US5406219A
公开(公告)日：1995-04-11
申请号：US16131
申请日：1993-02-10
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： H03F3/45 , H03K5/24 , H03K19/017 , H03K19/094 , H03K5/153
CPC分类号： H03F3/45076 , H03K19/01707 , H03K19/09432 , H03K5/2481
摘要： First and second transistors respectively receive differential input signals each having first and second logic levels and respectively produce resultant currents dependent upon the levels of the input signals. The transistors may be CMOS transistors of the n-type with substantially identical characteristics. The input signals may be introduced to the gates of these transistors and the resultant currents may be produced at the drains of these transistors. Third and fourth transistors may receive the resultant currents. The third and fourth transistors may be CMOS transistors of the n-type with substantially identical characteristics. The resultant voltage at the first transistor may be introduced in a modified form to the third and fourth transistors to regulate the resultant voltage introduced to the third transistor and to expedite the response of the fourth transistor. The modification may be an inversion of the resultant voltage at the first transistor, the inversion being produced by an amplifier-inverter in a servo loop with the third transistor. The currents on the drains of the first and second transistors may be respectively introduced to the sources of the third and fourth transistors. The modified (or inverted) voltage from the drain of the first transistor may be introduced to the gates of the third and fourth transistors. An output voltage may be provided at the source of the fourth transistor. The output voltage may be inverted as by an amplifier-inverter having characteristics substantially identical to those of the amplifier-inverter in the servo loop.
摘要翻译：第一和第二晶体管分别接收各自具有第一和第二逻辑电平的差分输入信号，并且分别产生取决于输入信号电平的合成电流。晶体管可以是具有基本相同特性的n型CMOS晶体管。输入信号可以被引入到这些晶体管的栅极，并且所得到的电流可以在这些晶体管的漏极处产生。第三和第四晶体管可以接收所得的电流。第三和第四晶体管可以是具有基本相同特性的n型CMOS晶体管。第一晶体管处的合成电压可以以修改形式引入第三和第四晶体管，以调节引入第三晶体管的合成电压并加速第四晶体管的响应。该修改可以是在第一晶体管处的合成电压的反转，反转由具有第三晶体管的伺服环路中的放大器 - 反相器产生。可以将第一和第二晶体管的漏极上的电流分别引入第三和第四晶体管的源极。来自第一晶体管的漏极的修正（或反转）电压可以被引入第三和第四晶体管的栅极。可以在第四晶体管的源极处提供输出电压。输出电压可以由具有与伺服环路中的放大器 - 反相器基本相同的特性的放大器 - 反相器反转。

70. 发明授权

US5227714A Voltage regulator 失效
标题翻译：电压稳压器
公开(公告)号：US5227714A
公开(公告)日：1993-07-13
申请号：US772218
申请日：1991-10-07
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： G05F1/56 , G05F1/46 , G05F3/24 , G05F3/26
CPC分类号： G05F3/24 , G05F1/465
摘要： A system for regulating an output voltage to a particular value includes a control transistor which produces an output voltage when energized by an energizing voltage. A voltage divider formed as by a pair of transistors with a particular ratio of transconductances divides the magnitude of this output voltage by a ratio related to the ratio of the transconductances. The transistors in the voltage divider may be respectively CMOS n- and p- transistors. The divided output voltage is introduced to a comparator (formed as from a pair of transistors) for comparison with a fixed reference voltage obtained as from a resistance ladder energized by the energizing voltage. The comparator introduces voltages to a comparator amplifier in accordance with such comparison. The comparator amplifier may include a transistor which produces changes in a current related to changes in the divided output voltage. The comparator amplifier may further include a current mirror which provides changes in a current related to changes in the current through the amplifier transistor. The current changes in the current mirror cause changes to be produced in a voltage (e.g. error voltage) from the current mirror. These error voltage changes are introduced to the control transistor to regulate the output voltage to the particular value.

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