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61. 发明授权

US09082515B2 Variable resistance nonvolatile memory device and driving method of variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件和可变电阻非易失性存储器件的驱动方法
公开(公告)号：US09082515B2
公开(公告)日：2015-07-14
申请号：US14113054
申请日：2012-05-24
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C29/00 , G11C13/00 , G11C29/52 , G11C29/50
CPC分类号： G11C29/70 , G11C13/004 , G11C13/0069 , G11C29/52 , G11C29/808 , G11C29/832 , G11C29/883 , G11C2029/5006 , G11C2213/15 , G11C2213/71 , G11C2213/72
摘要： A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state. Both the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in the inactive state.
摘要翻译：通过减少异常电流实现稳定运行。可变电阻非易失性存储器件包括：存储单元阵列，其具有各自包括串联连接的可变电阻元件和电流导向元件的存储单元，每个存储单元位于位之一的三维交叉点线路和字线之一，并且当施加超过预定阈值电压的电压时，假定当前的导向元件正在导通; 以及检测电路，其检测处于第二低电阻状态的电阻值低于第一低电阻状态下的电阻值的故障存储单元。连接到由检测电路检测到的故障存储单元的位线和字线均固定在不活动状态。

62. 发明授权

US08837200B2 Nonvolatile semiconductor memory device and read method for the same 有权
标题翻译：非易失性半导体存储器件及其读取方法相同
公开(公告)号：US08837200B2
公开(公告)日：2014-09-16
申请号：US13700346
申请日：2012-06-18
申请人： Kiyotaka Tsuji , Kazuhiko Shimakawa
发明人： Kiyotaka Tsuji , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C2013/0054 , G11C2213/77
摘要： A nonvolatile semiconductor memory device includes: word lines; bit lines formed so as to three-dimensionally cross the word lines; and a cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines. The cells include: a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal; and an offset detection cell having a constant resistance value that is higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory.
摘要翻译：非易失性半导体存储器件包括：字线; 形成为三维地跨越字线的位线; 以及包括各自提供在字线和位线的三维交叉点中的相应一个的单元的交叉点单元阵列。单元包括：存储单元，其包括通过基于电信号在至少两个状态之间可逆地改变电阻值而作为存储器操作的存储元件; 以及偏移检测单元，其具有比作为存储器操作时作为存储元件的状态的高电阻状态下的存储元件的电阻值高的恒定电阻值。

63. 发明授权

US08787070B2 Reference cell circuit and variable resistance nonvolatile memory device including the same 有权
标题翻译：参考单元电路和包括其的可变电阻非易失性存储器件
公开(公告)号：US08787070B2
公开(公告)日：2014-07-22
申请号：US13634292
申请日：2012-04-12
申请人： Kazuhiko Shimakawa
发明人： Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0002 , G11C7/14 , G11C13/0004 , G11C13/0009 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3418 , G11C2013/0054
摘要： Included are reference cells each including a variable resistance element which reversibly changes between a predetermined low resistance state LR and a predetermined high resistance state HR according to an application of an electric signal, a comparator which compares resistance values of the reference cells, a pulse generation circuit which generates an electric signal for setting the reference cells to LR or HR, and a control circuit which controls operations where application of the generated electric signal to one of the reference cells corresponding to a comparison result of the comparator and application of a new electric signal generated by the pulse generation circuit to one of the reference cells corresponding to a new comparison result of the comparator are repeated, and then one of the reference cells corresponding to a final comparison result of the comparator is connected to an output terminal.
摘要翻译：包括参考单元，每个参考单元包括根据电信号的应用在预定的低电阻状态LR和预定的高电阻状态HR之间可逆地变化的可变电阻元件，比较参考单元的电阻值的比较器，脉冲发生生成用于将参考单元设置为LR或HR的电信号的电路，以及控制电路，其控制将生成的电信号应用于与比较器的比较结果相对应的参考单元之一的工作，以及应用新的电重复由脉冲发生电路产生的对应于比较器的新比较结果的参考单元之一的信号，然后将与比较器的最终比较结果对应的参考单元中的一个连接到输出端子。

64. 发明申请

US20120044749A1 VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE AND METHOD OF FORMING MEMORY CELL 审中-公开
标题翻译：可变电阻非易失性存储器件及形成存储器单元的方法
公开(公告)号：US20120044749A1
公开(公告)日：2012-02-23
申请号：US13266932
申请日：2010-11-02
申请人： Shunsaku Muraoka , Yoshihiko Kanzawa , Takeshi Takagi , Kazuhiko Shimakawa
发明人： Shunsaku Muraoka , Yoshihiko Kanzawa , Takeshi Takagi , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , H01L21/8239 , H01L45/00
CPC分类号： H01L27/2436 , G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/79 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOx and MOy (where x
摘要翻译：一种可变电阻非易失性存储装置，包括：（i）半导体衬底（301），（ii）具有下电极和上电极（309a，309c）的可变电阻元件（309）和可变电阻层（309b），其电阻值基于各自具有不同极性的电压信号而被可逆地变化并施加在电极（309a，309c）之间，以及（iii）形成在基板上的MOS晶体管（301），其中所述可变电阻层（309b）包括：具有组成MOx和MOy（其中x

65. 发明授权

US08022502B2 Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor apparatus using the nonvolatile memory element 有权
标题翻译：非易失性存储元件及其制造方法以及使用非易失性存储元件的非易失性半导体装置
公开(公告)号：US08022502B2
公开(公告)日：2011-09-20
申请号：US12307211
申请日：2008-03-26
申请人： Yoshihiko Kanzawa , Koji Katayama , Satoru Fujii , Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Ryoko Miyanaga , Takeshi Takagi , Kazuhiko Shimakawa
发明人： Yoshihiko Kanzawa , Koji Katayama , Satoru Fujii , Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Ryoko Miyanaga , Takeshi Takagi , Kazuhiko Shimakawa
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1675 , Y10S438/90
摘要： A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0
摘要翻译：非易失性存储元件包括设置在第一电极层（103）和第二电极层（107）之间的第一电极层（103），第二电极（107）和电阻变化层（106），电阻电阻变化层的值根据施加在电极（103），（107）之间的具有不同极性的电信号而可逆地变化，其中电阻变化层（106）具有第一区域，该第一区域包括第一氧缺陷型氧化钽，由TaOx（0

66. 发明申请

US20100177555A1 VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE 有权
标题翻译：可变电阻非易失存储器件
公开(公告)号：US20100177555A1
公开(公告)日：2010-07-15
申请号：US12676933
申请日：2008-12-15
申请人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
发明人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
IPC分类号： G11C11/00 , H01L45/00 , G11C8/08
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt
摘要翻译：可变电阻非易失性存储装置包括通过串联连接可变电阻元件（309）形成的存储单元（300），该可变电阻元件（309）包括基于各自具有不同极性的电信号可逆地改变的可变电阻层（309b）和晶体管（307），包括半导体衬底（301）和两个N型扩散层区域（302a，302b），其中可变电阻层（309b）包括过渡金属的氧缺乏氧化物，下电极和上电极（309a， 309c）的材料由下部电极（309a）的标准电极电位V1，上部电极（309c）的标准电极电位V2，过渡金属的标准电极电位Vt满足Vt

67. 发明申请

US20100046270A1 RESISTANCE VARIABLE MEMORY APPARATUS 有权
标题翻译：电阻可变存储器
公开(公告)号：US20100046270A1
公开(公告)日：2010-02-25
申请号：US12514025
申请日：2007-11-16
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa , Zhiqiang Wei
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa , Zhiqiang Wei
IPC分类号： G11C17/00 , G11C11/00
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/76 , G11C2213/79
摘要： A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-resistance state.
摘要翻译：本发明的电阻可变存储装置（100）是电阻可变存储装置（100），其使用电阻可变元件（22），其响应于相同极性的电脉冲在多个电阻状态之间转变，其中串联电阻设定单元（10）被配置为设置串联电流路径的电阻值，并联电阻设定单元（30）被配置为设置并联电流路径的电阻值，使得电阻值成为节点电位在电阻可变元件（22）切换到高电阻状态之后电脉冲施加装置（50）输出第一电脉冲的状态下不大于第二电压电平，并且节点电位不大在电脉冲施加装置（50）在电阻可变元件（22）之后输出第二电脉冲的状态下的第一电压电平ha s切换到低电阻状态。

68. 发明授权

US08624214B2 Semiconductor device having a resistance variable element and a manufacturing method thereof 有权
标题翻译：具有电阻可变元件的半导体器件及其制造方法
公开(公告)号：US08624214B2
公开(公告)日：2014-01-07
申请号：US12866359
申请日：2009-06-08
申请人： Takumi Mikawa , Kazuhiko Shimakawa
发明人： Takumi Mikawa , Kazuhiko Shimakawa
IPC分类号： H01L29/02 , H01L47/00 , H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/34 , H01L27/24
摘要： A semiconductor device (100) of the present invention has a structure in which an interlayer insulating layer (115) is formed on an uppermost wire (114), contacts (116, 117) penetrate the interlayer insulating layer (115), a lower electrode (118a) of the resistance variable element is formed on the interlayer insulating layer (115) to cover the contact (116), and resistance variable layer (119) is formed on the interlayer insulating layer (115) to cover the lower electrode (118a) and the contact (117). The contact (116) and the lower electrode (118a) serve as a first terminal, while the contact (117) serves as a second terminal.
摘要翻译：本发明的半导体器件（100）具有层间绝缘层（115）形成在最上层导线（114）上的结构，触点（116,117）穿过层间绝缘层（115），下电极在层间绝缘层（115）上形成电阻可变元件（118a）以覆盖触点（116），并且在层间绝缘层（115）上形成电阻变化层（119）以覆盖下电极（118a））和触点（117）。触点（116）和下电极（118a）用作第一端子，而触头（117）用作第二端子。

69. 发明申请

US20130148407A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD FOR THE SAME 有权
标题翻译：非易失性半导体存储器件及其读取方法
公开(公告)号：US20130148407A1
公开(公告)日：2013-06-13
申请号：US13700346
申请日：2012-06-18
申请人： Kiyotaka Tsuji , Kazuhiko Shimakawa
发明人： Kiyotaka Tsuji , Kazuhiko Shimakawa
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C2013/0054 , G11C2213/77
摘要： A nonvolatile semiconductor memory device includes: word lines; bit lines formed so as to three-dimensionally cross the word lines; and a cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines. The cells include: a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal; and an offset detection cell having a constant resistance value that is higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory.
摘要翻译：非易失性半导体存储器件包括：字线; 形成为三维地跨越字线的位线; 以及包括各自提供在字线和位线的三维交叉点中的相应一个的单元的交叉点单元阵列。单元包括：存储单元，其包括通过基于电信号在至少两个状态之间可逆地改变电阻值而作为存储器操作的存储元件; 以及偏移检测单元，其具有比作为存储器操作时作为存储元件的状态的高电阻状态下的存储元件的电阻值高的恒定电阻值。

70. 发明授权

US08445319B2 Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor apparatus using the nonvolatile memory element 有权
标题翻译：非易失性存储元件及其制造方法以及使用非易失性存储元件的非易失性半导体装置
公开(公告)号：US08445319B2
公开(公告)日：2013-05-21
申请号：US13205408
申请日：2011-08-08
申请人： Yoshihiko Kanzawa , Koji Katayama , Satoru Fujii , Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Ryoko Miyanaga , Takeshi Takagi , Kazuhiko Shimakawa
发明人： Yoshihiko Kanzawa , Koji Katayama , Satoru Fujii , Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Ryoko Miyanaga , Takeshi Takagi , Kazuhiko Shimakawa
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1675 , Y10S438/90
摘要： A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0
摘要翻译：非易失性存储元件包括设置在第一电极层（103）和第二电极层（107）之间的第一电极层（103），第二电极（107）和电阻变化层（106），电阻电阻变化层的值根据施加在电极（103），（107）之间的具有不同极性的电信号而可逆地变化，其中电阻变化层（106）具有第一区域，该第一区域包括第一氧缺陷型氧化钽，由TaOx（0

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