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61. 发明申请

US20070032037A1 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration 有权
标题翻译：使用自组织原子迁移在体半导体衬底中形成SOI样结构的方法
公开(公告)号：US20070032037A1
公开(公告)日：2007-02-08
申请号：US11546768
申请日：2006-10-12
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

62. 发明申请

US20070013012A1 Etch-stop layer structure 审中-公开
标题翻译：蚀刻层结构
公开(公告)号：US20070013012A1
公开(公告)日：2007-01-18
申请号：US11180935
申请日：2005-07-13
申请人： Jhon-Jhy Liaw , Tze-Liang Lee
发明人： Jhon-Jhy Liaw , Tze-Liang Lee
IPC分类号： H01L29/772 , H01L21/469
CPC分类号： H01L21/76837 , H01L21/76834 , H01L21/823425
摘要： A semiconductor structure that includes a first gate structure, second gate structure and a nitrogen-containing etch-stop layer. The first gate structure whose sidewalls are bounded by at least one first spacer is formed on a semiconductor substrate. The second gate structure whose sidewalls are bounded by at least one second spacer is formed on the semiconductor substrate, wherein the second gate structure is adjacent to the first gate structure. The nitrogen-containing etch-stop layer is formed over the first and second gate structures, having a thickness substantially the same over the semiconductor substrate, thereby improving a step coverage of a subsequent layer formed on the nitrogen-containing etch-stop layer between the first and second gate structures.
摘要翻译：一种包括第一栅极结构，第二栅极结构和含氮蚀刻停止层的半导体结构。其侧壁由至少一个第一间隔物界定的第一栅极结构形成在半导体衬底上。其侧壁由至少一个第二间隔物限定的第二栅极结构形成在半导体衬底上，其中第二栅极结构与第一栅极结构相邻。含氮蚀刻停止层形成在第一和第二栅极结构之上，其厚度在半导体衬底上基本上相同，由此改善在含氮蚀刻停止层上形成的后续层的阶梯覆盖第一和第二门结构。

63. 发明申请

US20070010073A1 Method of forming a MOS device having a strained channel region 审中-公开
标题翻译：形成具有应变通道区域的MOS器件的方法
公开(公告)号：US20070010073A1
公开(公告)日：2007-01-11
申请号：US11175563
申请日：2005-07-06
申请人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
发明人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/76828 , H01L21/76829 , H01L21/823412 , H01L21/82345 , H01L21/823807 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer is provided. The method further includes pre-amorphizing the source/drain region before the super annealing. The strained capping layer may further be formed on a pre-amorphized gate electrode, and the gate electrode is super annealed. The strain is generated and preserved after the removal of the strained capping layer.
摘要翻译：一种形成半导体器件的方法，包括提供包括第一器件区域的衬底，在第一器件区域中注入源极/漏极区域，在源极/漏极区域上形成应变封盖层，超退火并使源极/漏极区域结晶并且提供基本上所有的应变封盖层的去除。该方法还包括在超退火之前对源极/漏极区进行非晶化。应变封盖层可以进一步形成在非晶化的栅电极上，并且栅电极被超退火。在去除应变封盖层后产生并保存菌株。

64. 发明申请

US20060246672A1 Method of forming a locally strained transistor 有权
标题翻译：形成局部应变晶体管的方法
公开(公告)号：US20060246672A1
公开(公告)日：2006-11-02
申请号：US11119522
申请日：2005-04-29
申请人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee
发明人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee
IPC分类号： H01L21/336 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/78 , H01L29/7843
摘要： A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.
摘要翻译：本发明的优选实施例提供半导体制造方法。一个实施例包括形成具有侧壁间隔物的MOS器件。高应力层沉积在器件上。在栅极电极和侧壁间隔物上的层的该部分中选择性地调节应力。优选地，栅极上方和侧壁间隔物上的应力层从第一应力调整到第二应力，其中第一应力是拉伸和压缩之一，第二应力是拉伸和压缩中的另一个。优选实施例在PMOS和NMOS沟道区域内选择性地诱发适当的应力，以改善它们各自的载流子迁移率。本发明的其它实施例包括具有上覆应力层的场效应晶体管（FET），所述应力层由不同的应力区域组成。

65. 发明申请

US20060228850A1 Pattern loading effect reduction for selective epitaxial growth 审中-公开
标题翻译：用于选择性外延生长的图案加载效应降低
公开(公告)号：US20060228850A1
公开(公告)日：2006-10-12
申请号：US11100053
申请日：2005-04-06
申请人： Pang-Yen Tsai , Chih-Chien Chang , Indira Yang , Tze-Liang Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Chih-Chien Chang , Indira Yang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66628
摘要： A method of reducing the pattern-loading effect for selective epitaxial growth. The method includes the steps of: forming a mask layer over a substrate; forming an isolation region in the substrate isolating an active region and a dummy active region; removing at least a portion of the mask layer in the active region and thus forming a first opening, the substrate being exposed through the first opening; removing at least a portion of the mask layer in the dummy active region and thus forming a second opening, the substrate being exposed through the second opening; and performing selective epitaxial growth simultaneously on the substrate in the first opening and second openings. By introducing the second opening wherein epitaxial growth occurs, the pattern density is more uniform and thus the pattern-loading effect is reduced.
摘要翻译：降低选择性外延生长的图案负载效应的方法。该方法包括以下步骤：在衬底上形成掩模层; 在所述衬底中形成隔离有源区和虚拟有源区的隔离区; 去除所述有源区域中的所述掩模层的至少一部分，从而形成第一开口，所述基板通过所述第一开口露出; 去除所述虚拟有源区域中的所述掩模层的至少一部分，从而形成第二开口，所述基板通过所述第二开口露出; 以及在所述第一开口和所述第二开口中的所述衬底上同时执行选择性外延生长。通过引入其中发生外延生长的第二开口，图案密度更均匀，因此图案加载效应降低。

66. 发明申请

US20060113282A1 Method of depositing an epitaxial layer of SiGe subsequent to a plasma etch 有权
公开(公告)号：US20060113282A1
公开(公告)日：2006-06-01
申请号：US11001384
申请日：2004-12-01
申请人： Chih-Chien Chang , Shun Lin , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
发明人： Chih-Chien Chang , Shun Lin , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： B44C1/22 , B08B6/00 , B08B3/00 , C03C25/68
CPC分类号： H01L21/02658 , H01L21/02381 , H01L21/02532
摘要： A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.

67. 发明申请

US20060099771A1 Selective nitride liner formation for shallow trench isolation 有权
标题翻译：用于浅沟槽隔离的选择性氮化物衬垫形成
公开(公告)号：US20060099771A1
公开(公告)日：2006-05-11
申请号：US10970090
申请日：2004-10-21
申请人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.
摘要翻译：一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

68. 发明申请

US20060094194A1 Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology 审中-公开
标题翻译：用于低于90NM CMOS技术的低温高应力氮化膜的高级一次性间隔工艺
公开(公告)号：US20060094194A1
公开(公告)日：2006-05-04
申请号：US10982115
申请日：2004-11-04
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy sidewall spacers, and the source and drain, performing a first anneal, and removing the capping layer and the dummy sidewall spacers.
摘要翻译：一种形成半导体器件的方法包括提供栅电极，其具有形成在衬底中的暴露的侧壁，在栅极电极暴露的侧壁上形成虚设间隔物，执行第一注入以形成源极和漏极注入，在栅极上形成覆盖层电极，虚拟侧壁间隔物以及源极和漏极，执行第一退火，以及去除覆盖层和虚设侧壁间隔物。

69. 发明授权

US06933157B2 Semiconductor wafer manufacturing methods employing cleaning delay period 有权
标题翻译：采用清洁延迟期的半导体晶圆制造方法
公开(公告)号：US06933157B2
公开(公告)日：2005-08-23
申请号：US10712460
申请日：2003-11-13
申请人： Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/00 , H01L21/02 , H01L21/44
CPC分类号： H01L21/02052 , Y10S438/906
摘要： A method of manufacturing a semiconductor wafer including cleaning a surface of the wafer during a first time period and forming a layer over the surface during a second time period. The first time period includes a cleaning delay period prior to a cleaning portion of the first time period, the cleaning delay period configured such that an end time of the first time period substantially coincides with a start time of the second time period.
摘要翻译：一种制造半导体晶片的方法，包括在第一时间段期间清洁所述晶片的表面，并且在第二时间段期间在所述表面上形成层。第一时间段包括在第一时间段的清洁部分之前的清洁延迟时间，清洁延迟时间被配置为使得第一时间段的结束时间基本上与第二时间段的开始时间一致。

70. 发明申请

US20050151239A1 Integrated circuit devices, edge seals therefor 有权
标题翻译：集成电路器件，边缘封装
公开(公告)号：US20050151239A1
公开(公告)日：2005-07-14
申请号：US11002098
申请日：2004-12-03
申请人： Tze-Liang Lee
发明人： Tze-Liang Lee
IPC分类号： H01L21/78 , H01L23/04 , H01L23/58
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An edge seal for a chip with integrated circuits. A first metal line extends along a periphery of the chip, with a first inter-metal dielectric layer on the first metal line. A second metal line overlies the first inter-metal dielectric layer and extends along the periphery of the chip. A plurality of first metal plugs in the first inter-metal dielectric layer connects the first metal line and the second metal line and at least one first metal wall in the first inter-metal dielectric layer is laterally adjacent to a periphery of the first metal line.
摘要翻译：用于具有集成电路的芯片的边缘密封。第一金属线沿着芯片的周边延伸，在第一金属线上具有第一金属间介电层。第二金属线覆盖在第一金属间介电层上并且沿着芯片的周边延伸。第一金属间电介质层中的多个第一金属插塞连接第一金属线和第二金属线，并且第一金属间介电层中的至少一个第一金属壁横向邻近于第一金属线的周边。

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