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1. 发明授权

US07361572B2 STI liner modification method 有权
标题翻译： STI衬垫修改方法
公开(公告)号：US07361572B2
公开(公告)日：2008-04-22
申请号：US11059728
申请日：2005-02-17
申请人： Chien-Hao Chen , Vincent S. Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Vincent S. Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/76235
摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.
摘要翻译：公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化的衬里氧化物层。本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

2. 发明授权

US07259050B2 Semiconductor device and method of making the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07259050B2
公开(公告)日：2007-08-21
申请号：US10834474
申请日：2004-04-29
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
IPC分类号： H01L21/338
CPC分类号： H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.
摘要翻译：半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿蚀刻速率。

3. 发明申请

US20060094194A1 Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology 审中-公开
标题翻译：用于低于90NM CMOS技术的低温高应力氮化膜的高级一次性间隔工艺
公开(公告)号：US20060094194A1
公开(公告)日：2006-05-04
申请号：US10982115
申请日：2004-11-04
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy sidewall spacers, and the source and drain, performing a first anneal, and removing the capping layer and the dummy sidewall spacers.
摘要翻译：一种形成半导体器件的方法包括提供栅电极，其具有形成在衬底中的暴露的侧壁，在栅极电极暴露的侧壁上形成虚设间隔物，执行第一注入以形成源极和漏极注入，在栅极上形成覆盖层电极，虚拟侧壁间隔物以及源极和漏极，执行第一退火，以及去除覆盖层和虚设侧壁间隔物。

4. 发明申请

US20050136583A1 Advanced strained-channel technique to improve CMOS performance 审中-公开
标题翻译：先进的应变通道技术，以提高CMOS性能
公开(公告)号：US20050136583A1
公开(公告)日：2005-06-23
申请号：US10744746
申请日：2003-12-23
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823842
摘要： A method of improving CMOS device performance, comprising the following steps. A structure having a gate electrode formed thereover and a channel formed thereunder is provided. The gate electrode having an initial lower width and an initial upper width. A capping layer having a tensile stress is formed over the structure and the gate electrode. The gate electrode is annealed to achieve tensile stress in the channel.
摘要翻译：一种提高CMOS器件性能的方法，包括以下步骤。提供了具有形成在其上的栅电极和在其下形成的沟道的结构。栅电极具有初始下宽度和初始上宽度。在结构和栅电极上形成具有拉伸应力的覆盖层。栅电极退火以在通道中实现拉伸应力。

5. 发明授权

US07316970B2 Method for forming high selectivity protection layer on semiconductor device 有权
标题翻译：在半导体器件上形成高选择性保护层的方法
公开(公告)号：US07316970B2
公开(公告)日：2008-01-08
申请号：US10892014
申请日：2004-07-14
申请人： Chien-Hao Chen , Ju-Wang Hsu , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Ju-Wang Hsu , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/425
CPC分类号： H01L21/31111 , H01L21/823481 , H01L29/665 , H01L29/6656 , H01L29/78
摘要： A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.
摘要翻译：在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。在半导体衬底上形成隔离结构。在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。形成光致抗蚀剂掩模以部分覆盖原始氮化物层。执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。

6. 发明申请

US20060049470A1 Double layer polysilicon gate electrode 审中-公开
标题翻译：双层多晶硅栅电极
公开(公告)号：US20060049470A1
公开(公告)日：2006-03-09
申请号：US10936271
申请日：2004-09-07
申请人： Chia-Lin Chen , Ming-Jie Huang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chia-Lin Chen , Ming-Jie Huang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/76
CPC分类号： H01L29/4925 , H01L21/28035 , H01L29/665
摘要： A method for forming a microelectronic product and the microelectronic product resulting from the method both employ a bilayer gate electrode. The bilayer gate electrode employs: (1) a first layer formed of a random oriented polycrystalline silicon material; and (2) a second layer laminated to the first layer and formed of a columnar oriented polycrystalline silicon material. The gate electrode provides enhanced performance to a semiconductor device within which it is formed.
摘要翻译：形成微电子产物的方法和由该方法得到的微电子产物都采用双层栅电极。双层栅极采用：（1）由随机取向的多晶硅材料形成的第一层; 和（2）层压到第一层并由柱状取向的多晶硅材料形成的第二层。栅电极为其形成的半导体器件提供增强的性能。

7. 发明申请

US20050159008A1 High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer 有权
标题翻译：栅极绝缘体层的高温氢退火以增加导电栅极结构和栅极绝缘体层之间的蚀刻选择性
公开(公告)号：US20050159008A1
公开(公告)日：2005-07-21
申请号：US10758317
申请日：2004-01-15
申请人： Vincent Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
发明人： Vincent Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/311 , H01L21/314 , H01L21/3213 , H01L21/336 , H01L21/477 , H01L29/51
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L21/32137 , H01L29/6659
摘要： A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.
摘要翻译：已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。

8. 发明授权

US07166525B2 High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer 有权
标题翻译：栅极绝缘体层的高温氢退火以增加导电栅极结构和栅极绝缘体层之间的蚀刻选择性
公开(公告)号：US07166525B2
公开(公告)日：2007-01-23
申请号：US10758317
申请日：2004-01-15
申请人： Vincent S. Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
发明人： Vincent S. Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L21/32137 , H01L29/6659
摘要： A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.
摘要翻译：已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。

9. 发明申请

US20060223255A1 Method for selectively stressing MOSFETs to improve charge carrier mobility 审中-公开
标题翻译：选择性地强迫MOSFET以改善载流子迁移率的方法
公开(公告)号：US20060223255A1
公开(公告)日：2006-10-05
申请号：US11370397
申请日：2006-03-07
申请人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.
摘要翻译：一种具有改善的电荷迁移率的应变通道MOSFET器件及其形成方法，所述方法包括在衬底上提供具有半导体导电类型的第一半导体导电类型的第一栅极和第二栅极; 在所述第一栅极上形成具有第一类型应力的第一应变层; 并且在所述第二浇口上形成具有第二类型应力的第二应变层。

10. 发明申请

US20060183292A1 STI liner modification method 有权
标题翻译： STI衬垫修改方法
公开(公告)号：US20060183292A1
公开(公告)日：2006-08-17
申请号：US11059728
申请日：2005-02-17
申请人： Chien-Hao Chen , Vincent Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Vincent Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/76235
摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.
摘要翻译：公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化的衬里氧化物层。本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

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