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61. 发明授权

US07012009B2 Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process 失效
标题翻译：使用新型双温工艺改善硅/氧化物/多晶硅表面的硅 - 锗膜的电连续性的方法
公开(公告)号：US07012009B2
公开(公告)日：2006-03-14
申请号：US10785524
申请日：2004-02-24
申请人： Kuen-Chyr Lee , Liang-Gi Yao , Tien-Chih Chang , Chia-Lin Chen , Shih-Chang Chen , Mong-Song Liang
发明人： Kuen-Chyr Lee , Liang-Gi Yao , Tien-Chih Chang , Chia-Lin Chen , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/0245 , H01L21/02532
摘要： A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with shorter reaction times, and then growing an epitaxial Si—Ge layer with a Si cap layer at a lower temperature to form the intrinsic base with low boron out-diffusion. This results in an HBT having the desired narrow base profile while minimizing the discontinuities (voids) in the Si—Ge layer over the insulator to provide good electrical contacts and uniformity to the intrinsic base.
摘要翻译：在异质结双极晶体管的基极的基板上制造改进的硅 - 锗层的方法是使用双温工艺实现的。该方法包括在更高的温度下生长种子层以在较短的反应时间下降低晶粒尺寸，然后在较低温度下生长具有Si覆盖层的外延Si-Ge层以形成具有低硼外扩散的本征碱。这导致HBT具有期望的窄基底轮廓，同时最小化绝缘体上的Si-Ge层中的不连续性（空隙），以提供良好的电接触和对本征基底的均匀性。

62. 发明申请

US20060027925A1 Composite barrier layer 有权
标题翻译：复合阻挡层
公开(公告)号：US20060027925A1
公开(公告)日：2006-02-09
申请号：US11024916
申请日：2004-12-28
申请人： Cheng-Lin Huang , Ching-Hua Hsieh , Hsien-Ming Lee , Shing-Chyang Pan , Chao-Hsien Peng , Li-Lin Su , Jing-Cheng Lin , Shao-Lin Shue , Mong-Song Liang
发明人： Cheng-Lin Huang , Ching-Hua Hsieh , Hsien-Ming Lee , Shing-Chyang Pan , Chao-Hsien Peng , Li-Lin Su , Jing-Cheng Lin , Shao-Lin Shue , Mong-Song Liang
IPC分类号： H01L29/788
CPC分类号： H01L21/76844 , H01L21/76846 , H01L21/76862 , Y10S438/927
摘要： A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.
摘要翻译：当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。

63. 发明申请

US20050245035A1 Method for producing low defect density strained -Si channel MOSFETS 有权
标题翻译：低缺陷密度应变-Si沟道MOSFET的制造方法
公开(公告)号：US20050245035A1
公开(公告)日：2005-11-03
申请号：US10838721
申请日：2004-05-03
申请人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
发明人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/20 , H01L21/205 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L29/665 , H01L29/78
摘要： A silicon strained channel MOSFET device and method for forming the same the method providing improved wafer throughput and low defect density including the steps of providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane.
摘要翻译：一种硅应变通道MOSFET器件及其形成方法，该方法提供提供晶片生产能力和低缺陷密度的方法，包括提供硅衬底的步骤; 使用选自乙硅烷，丙硅烷，二氯硅烷和硅烷的至少一种沉积前体外延生长第一硅层; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长阶梯级SiGe缓冲层并使第一硅层接触; 使用至少一种选自乙硅烷和丙硅烷的沉积前体外延生长SiGe覆盖层并使其与阶级SiGe缓冲层接触; 并且使用至少一种选自乙硅烷，丙硅烷，二氯硅烷和硅烷的沉积前体外延生长第二硅层。

64. 发明申请

US20050215052A1 Integrated treatment method for obtaining robust low dielectric constant materials 失效
标题翻译：用于获得坚固的低介电常数材料的综合处理方法
公开(公告)号：US20050215052A1
公开(公告)日：2005-09-29
申请号：US10810970
申请日：2004-03-26
申请人： Mong-Song Liang , Yung-Cheng Lu , Huilin Chang
发明人： Mong-Song Liang , Yung-Cheng Lu , Huilin Chang
IPC分类号： H01L21/3105 , H01L21/44 , H01L21/76 , H01L21/768
CPC分类号： H01L21/76826 , H01L21/3105 , H01L21/76825 , H01L21/76828
摘要： An integrated method comprises providing a low dielectric material, applying a first treatment altering a first property of the low dielectric material, and applying a second treatment altering a second property of the treated low dielectric material and producing a lower dielectric material with better mechanical stability.
摘要翻译：集成方法包括提供低电介质材料，施加改变低电介质材料的第一特性的第一处理，以及施加改变所处理的低电介质材料的第二特性并产生具有更好的机械稳定性的较低电介质材料的第二处理。

65. 发明申请

US20050176229A1 NOVEL DEPOSITION METHOD FOR SI-GE EPI LAYER ON DIFFERENT INTERMEDIATE SUBSTRATES 有权
标题翻译：在不同中间基板上的SI-GE EPI层的新型沉积方法
公开(公告)号：US20050176229A1
公开(公告)日：2005-08-11
申请号：US10772939
申请日：2004-02-05
申请人： Liang-Gi Yao , Kuen-Chyr Lee , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Kuen-Chyr Lee , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/331
CPC分类号： H01L29/66242 , H01L21/02532 , H01L21/02579 , H01L21/0262 , Y10S438/918
摘要： A method of forming an Si—Ge epitaxial layer comprising the following steps. A structure is provided and a doped Si—Ge seed layer is formed thereover. The doped Si—Ge seed layer having increased nucleation sites. A Si—Ge epitaxial layer upon the doped Si—Ge seed layer whereby the Si—Ge epitaxial layer lacks discontinuity.
摘要翻译：一种形成Si-Ge外延层的方法，包括以下步骤。提供一种结构，并在其上形成掺杂的Si-Ge种子层。掺杂的Si-Ge种子层具有增加的成核位点。在掺杂Si-Ge晶种层上的Si-Ge外延层，由此Si-Ge外延层缺少不连续性。

66. 发明授权

US06706629B1 Barrier-free copper interconnect 有权
标题翻译：无障碍铜互连
公开(公告)号：US06706629B1
公开(公告)日：2004-03-16
申请号：US10338120
申请日：2003-01-07
申请人： Jing-Cheng Lin , Cheng-Lin Huang , Winston Shue , Mong-Song Liang
发明人： Jing-Cheng Lin , Cheng-Lin Huang , Winston Shue , Mong-Song Liang
IPC分类号： H01L2144
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76831 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76888 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.
摘要翻译：提供了一种新的方法来产生包括铜的金属互连。本发明的第一实施例提供了铜掺杂层的应用。本发明的第二个实施例提供了在介质层中形成的开口的表面上沉积作为隔离膜的氮化硅层，然后从开口的底部去除氮化硅层，随后沉积在该开口的表面上的铜掺杂合金种子层，然后在铜合金种子层上镀一层铜。

67. 发明授权

US06555474B1 Method of forming a protective layer included in metal filled semiconductor features 有权
标题翻译：包含在金属填充的半导体特征中的保护层的形成方法
公开(公告)号：US06555474B1
公开(公告)日：2003-04-29
申请号：US10060820
申请日：2002-01-29
申请人： Cheng Lin Huang , Minghsing Tsai , Winston Shue , Mong-Song Liang
发明人： Cheng Lin Huang , Minghsing Tsai , Winston Shue , Mong-Song Liang
IPC分类号： H01L2144
CPC分类号： H01L21/76834 , H01L21/76843 , H01L21/76849 , H01L21/76852 , H01L21/76867 , H01L21/76873
摘要： A method of forming a protective layer included in a metal filled semiconductor feature including providing a substrate including an insulating dielectric material having an anisotropically etched opening for forming a semiconductor feature; conformally depositing over the semiconductor feature at least one metal layer to substantially fill the semiconductor feature at least a portion of the at least one metal layer containing dopant impurities; and, thermally treating the substrate for a time period sufficient to redistribute the dopant impurities to preferentially collect along the periphery of the at least one metal layer.
摘要翻译：一种形成包含在金属填充的半导体特征中的保护层的方法，包括提供包括具有用于形成半导体特征的各向异性蚀刻开口的绝缘介电材料的基板; 在所述半导体特征上共形沉积至少一个金属层以基本上填充所述至少一部分所述至少一个含有掺杂杂质的金属层的所述半导体特征; 并且将衬底热处理足以重新分布掺杂剂杂质的时间段，以优先地沿着至少一个金属层的周边收集。

68. 发明授权

US06476460B1 Stacked gate MOS structure for multiple voltage power supply applications 有权
标题翻译：用于多电压电源应用的堆叠门MOS结构
公开(公告)号：US06476460B1
公开(公告)日：2002-11-05
申请号：US09514845
申请日：2000-02-28
申请人： Mong-Song Liang , Jin-Yuan Lee , Choe-San Yoo
发明人： Mong-Song Liang , Jin-Yuan Lee , Choe-San Yoo
IPC分类号： H01L2900
CPC分类号： H01L28/40
摘要： A capacitor structure is formed on a semiconductor substrate to provide split voltages for semiconductor circuits. An active area is formed in the substrate serving as a lower capacitor plate for a bottom capacitor. A thin dielectric layer and field oxide regions are formed on the substrate, and the dielectric layer is covered with a capacitor plate over the active area to complete the bottom capacitor. A thick dielectric layer is formed over the device and a via is formed through the thick dielectric layer to the upper capacitor plate. A second lower plate is formed for a top capacitor. An inter-layer dielectric layer is formed over the second lower plate. An upper capacitor layer is formed over the inter-layer dielectric layer to form a top capacitor with a different capacitance value from the bottom capacitor. The value of the capacitance can be varied by selection of the permittivity and/or thickness of the dielectric layer and by variation of the effective plate area of the top and bottom capacitors.
摘要翻译：在半导体衬底上形成电容器结构，以提供半导体电路的分压。在用作底部电容器的下电容器板的衬底中形成有源区。在基板上形成薄的电介质层和场氧化物区域，并且在有源区域上用电容器板覆盖电介质层以完成底部电容器。在器件上形成厚的电介质层，并且通过厚电介质层形成通孔到上电容器板。形成顶部电容器的第二下板。在第二下板上形成层间电介质层。在层间电介质层上形成上层电容层，形成与底层电容器不同的电容值的顶层电容器。可以通过选择介电层的介电常数和/或厚度以及顶部和底部电容器的有效平板面积的变化来改变电容的值。

69. 发明授权

US06436771B1 Method of forming a semiconductor device with multiple thickness gate dielectric layers 有权
标题翻译：形成具有多个厚度栅极电介质层的半导体器件的方法
公开(公告)号：US06436771B1
公开(公告)日：2002-08-20
申请号：US09902895
申请日：2001-07-12
申请人： Syun-Ming Jang , Chen-Hua Yu , Mong-Song Liang
发明人： Syun-Ming Jang , Chen-Hua Yu , Mong-Song Liang
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： Process sequences used to simultaneously form a first dielectric gate layer for a first group of MOSFET elements, and a second dielectric gate layer for a second group of MOSFET elements, with the thickness of the first dielectric gate layer different than the thickness of the second gate dielectric layer, has been developed. A first iteration of this invention entails a remote plasma nitridization procedure used to form a thin silicon nitride layer on a bare, first portion of a semiconductor substrate, while simultaneously forming a thin silicon oxynitride layer on the surface of a first silicon dioxide layer, located on second portion of the semiconductor substrate. A thermal oxidation procedure than results in the formation of a thin second silicon dioxide layer, on the first portion of the semiconductor substrate, underlying the thin silicon nitride layer, while the first silicon dioxide layer, underlying the silicon oxynitride component of the composite dielectric layer, only increases slightly in thickness. A second iteration of this invention features the formation of a silicon nitride—first silicon dioxide, composite gate layer, on a first portion of a semiconductor substrate, with the composite gate layer used to retard oxidation during a thermal oxidation procedure used growth to form a second silicon dioxide layer, on a second portion of the semiconductor substrate.
摘要翻译：用于同时形成用于第一组MOSFET元件的第一电介质栅极层和用于第二组MOSFET元件的第二电介质栅极层的工艺序列，其中第一电介质栅极层的厚度不同于第二栅极的厚度电介质层，已经开发。本发明的第一次迭代需要用于在半导体衬底的裸露的第一部分上形成薄氮化硅层的远程等离子体氮化过程，同时在第一二氧化硅层的表面上形成薄的氮氧化硅层，所述第一二氧化硅层位于在半导体衬底的第二部分上。一种热氧化方法，其结果是在半导体衬底的第一部分上形成薄的第二二氧化硅层，位于薄氮化硅层下面，同时第一二氧化硅层位于复合介电层的氮氧化硅组分下面，厚度仅略有增加。本发明的第二次迭代的特征在于在半导体衬底的第一部分上形成氮化硅 - 第一二氧化硅复合栅极层，其中用于在热氧化过程中延迟氧化的复合栅极层用于生长以形成第二二氧化硅层，在半导体衬底的第二部分上。

70. 发明授权

US06423625B1 Method of improving the bondability between Au wires and Cu bonding pads 有权
标题翻译：提高Au线和Cu焊盘之间的粘接性的方法
公开(公告)号：US06423625B1
公开(公告)日：2002-07-23
申请号：US09385754
申请日：1999-08-30
申请人： Syun-Ming Jang , Mong-Song Liang , Chen-Hua Yu , Chung-Shi Liu , Jane-Bai Lai
发明人： Syun-Ming Jang , Mong-Song Liang , Chen-Hua Yu , Chung-Shi Liu , Jane-Bai Lai
IPC分类号： H01L2160
CPC分类号： H01L24/05 , H01L23/53238 , H01L24/03 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05001 , H01L2224/05006 , H01L2224/05083 , H01L2224/05147 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48647 , H01L2224/48699 , H01L2224/48724 , H01L2224/48747 , H01L2924/01007 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： Cu, for its rather loe resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.
摘要翻译：铜，因其相当的电阻率，将广泛应用于二分之一微米级ULSI器件。然而，众所周知，Cu在空气中容易被腐蚀。在芯片的封装中，由此制成Cu的焊盘将氧化。此外，Au球和Cu垫之间的反应非常差。另一方面，厚度约3-4nm的天然AlOx层将在Al中暴露于空气中形成; 形成的层是惰性的并且能够保护Al免于腐蚀。此外，Au球和Al之间的反应非常好。因此，利用本发明的方法，在用于成功的Au布线的Cu焊盘上实施作为胶水和保护层的Al或AlCu。

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