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61. 发明授权

US5257361A Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation 失效
标题翻译：用于使用虚拟存储方案和物理到虚拟地址转换来控制一个或多个分层存储器的方法和装置
公开(公告)号：US5257361A
公开(公告)日：1993-10-26
申请号：US603620
申请日：1990-10-26
申请人： Toshio Doi , Takeshi Takemoto , Yasuhiro Nakatsuka
发明人： Toshio Doi , Takeshi Takemoto , Yasuhiro Nakatsuka
IPC分类号： G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/0808 , G06F12/1063
摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.
摘要翻译：用于多处理器系统的集成电路结构的处理装置包括基于虚拟存储方案操作的执行单元和具有来自执行单元的逻辑地址指定的条目的高速缓冲存储器。为了控制高速缓冲存储器，提供包含与高速缓冲存储器相同的逻辑地址指定的条目并存储用于高速缓存存储器的对应条目的控制信息的第一地址阵列与具有由物理地址指定的条目的第二地址阵列相关联，将用于翻译物理地址的翻译信息存储到条目的逻辑地址。当响应于外部提供的高速缓冲存储器无效请求输入要执行无效的物理地址时，通过使用物理地址对第二地址阵列进行访问，以从第二地址阵列获得翻译信息，从而生成一个无效的逻辑地址。通过使用所生成的逻辑地址对控制信息进行无效处理来访问第一地址阵列。

62. 发明申请

US20110096667A1 PACKET COMMUNICATION DEVICE, PACKET COMMUNICATION SYSTEM, PACKET COMMUNICATION MODULE, DATA PROCESSOR, AND DATA TRANSFER SYSTEM 有权
标题翻译：分组通信设备，分组通信系统，分组通信模块，数据处理器和数据传输系统
公开(公告)号：US20110096667A1
公开(公告)日：2011-04-28
申请号：US12873893
申请日：2010-09-01
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
IPC分类号： H04L12/28 , H04L12/26
CPC分类号： H04L47/6255 , H04L12/44 , H04L47/10 , H04L47/2458 , H04L47/30 , H04L47/522 , H04L49/205 , H04L49/3018 , H04L49/351
摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.
摘要翻译：由CPU1生成的发送包被保存在缓冲器100a（100b）中。从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于传输分组的传输分组优先于传送分组传送到以太网820a或820b。这防止了传送缓冲器装置溢出。

63. 发明授权

US07676651B2 Micro controller for decompressing and compressing variable length codes via a compressed code dictionary 失效
标题翻译：微控制器，用于通过压缩代码字典对可变长度代码进行解压缩和压缩
公开(公告)号：US07676651B2
公开(公告)日：2010-03-09
申请号：US10611315
申请日：2003-06-30
申请人： Hiromichi Yamada , Yuichi Abe , Yasuhiro Nakatsuka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Yuichi Abe , Yasuhiro Nakatsuka , Takanaga Yamazaki
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30178
摘要： The invention provides a code compression technology that is favorable for a micro controller or other embedded system, and for compressed codes, resulting from conversion of program codes into variable length codes, and grouped program codes, address conversion information for specifying the start address of each group and compressed code type information for specifying the code length of each compressed code contained in a group are stored in a memory, and by enabling a corresponding compressed code address to be calculated from a code address output by a CPU, code compression that is favorable for a micro controller or other embedded system is realized.
摘要翻译：本发明提供了一种有利于微控制器或其他嵌入式系统的代码压缩技术，以及由程序代码转换为可变长度代码而导致的压缩代码，以及分组程序代码，用于指定每个的开始地址的地址转换信息用于指定包含在组中的每个压缩代码的代码长度的组和压缩代码类型信息被存储在存储器中，并且通过使得能够根据CPU输出的代码地址来计算相应的压缩代码地址，这是有利的代码压缩实现微控制器或其他嵌入式系统。

64. 发明授权

US07570748B2 Control and monitoring telecommunication system and method of setting a modulation method 失效
标题翻译：控制和监测电信系统和设置调制方法
公开(公告)号：US07570748B2
公开(公告)日：2009-08-04
申请号：US11018355
申请日：2004-12-22
申请人： Yoshikazu Ishii , Setsuo Arita , Yuji Ichinose , Nao Saito , Daisuke Sinma , Yasuhiro Nakatsuka
发明人： Yoshikazu Ishii , Setsuo Arita , Yuji Ichinose , Nao Saito , Daisuke Sinma , Yasuhiro Nakatsuka
IPC分类号： H04M11/06
CPC分类号： H04L5/0094 , H04L5/0007 , H04L5/0037 , H04L5/0046 , H04L5/006
摘要： Using a network in which one master station modem 105 and multiple slave station modem 106, 107, 108 are physically connected by rudder connection or bus connection with a telecommunication line 121, the measurement result of the S/N ratio between the master station and slave stations is once collected in the master station at the initialization stage, pairs of the modulation method, by which all modems can demodulate at high probability, and transmission voltage are calculated based on this data, and the calculation is transmitted to all slave stations; and at a normal transmission stage, information regarding the coordination and control of the network is transmitted in accordance with this setting. Thus, one-to-multi communication is realized, guaranteeing an access right.
摘要翻译：使用其中一个主站调制解调器105和多个从站调制解调器106,107,108通过与电信线路121的舵连接或总线连接物理连接的网络，主站和从站之间的S / N比的测量结果在初始化阶段，主站一旦收集站，则可以根据该数据计算出所有调制解调器可以以高概率解调的调制方式对和传输电压，并将计算发送到所有从站; 并且在正常发送阶段，根据该设置发送关于网络的协调和控制的信息。因此，实现一对多通信，保证访问权限。

65. 发明申请

US20090092147A1 Packet communication device, packet communication system, packet communication system, packet communication module, data processor, and data transfer system 有权
标题翻译：分组通信设备，分组通信系统，分组通信系统，分组通信模块，数据处理器和数据传输系统
公开(公告)号：US20090092147A1
公开(公告)日：2009-04-09
申请号：US12010762
申请日：2008-01-29
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Tasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Tasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
IPC分类号： H04L12/28
CPC分类号： H04L47/6255 , H04L12/44 , H04L47/10 , H04L47/2458 , H04L47/30 , H04L47/522 , H04L49/205 , H04L49/3018 , H04L49/351
摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.
摘要翻译：由CPU1生成的发送包被保存在缓冲器100a（100b）中。从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于传输分组的传输分组优先于传送分组传送到以太网820a或820b。这防止了传送缓冲器装置溢出。

66. 发明授权

US07064756B2 Data processing apparatus and shading apparatus 失效
公开(公告)号：US07064756B2
公开(公告)日：2006-06-20
申请号：US10947275
申请日：2004-09-23
申请人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
发明人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
IPC分类号： G06T11/00
CPC分类号： G06T1/60 , G06T11/40 , G06T15/50 , G06T15/80
摘要： In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.

67. 发明申请

US20050068897A1 Packet communication apparatus 有权
标题翻译：分组通信装置
公开(公告)号：US20050068897A1
公开(公告)日：2005-03-31
申请号：US10921879
申请日：2004-08-20
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Kotaro Shimamura , Yasuwo Watanabe
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Kotaro Shimamura , Yasuwo Watanabe
IPC分类号： H04L12/70 , G06F13/00 , H04L1/00 , H04L29/06 , H04M11/00
CPC分类号： H04L69/16 , H04L49/90 , H04L69/161 , H04L69/162 , H04L69/22
摘要： A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.
摘要翻译：包括CPU，存储器和分组通信电路的分组通信装置充当远程监视和控制受控对象的网络连接受控对象和网络终端之间的接口，并且在受控对象和网络终端还包括作为用于执行校验和计算以检查分组错误和复制操作的硬件单元的复制和操作单元。复制和操作单元在存储器中形成并由分组通信电路使用的发送缓冲器/接收缓冲器与由通信处理程序使用的工作区域之间同时执行分组数据复制操作和校验和计算，从而减少加载CPU并增加通信处理速度。

68. 发明授权

US06731291B2 Image processing device and system using the same 失效
公开(公告)号：US06731291B2
公开(公告)日：2004-05-04
申请号：US10054862
申请日：2002-01-25
申请人： Yasuhiro Nakatsuka , Keisuke Nakashima , Shigeru Matsuo , Masahisa Narita , Koyo Katsura , Hidehito Takewa , Tomoaki Aoki
发明人： Yasuhiro Nakatsuka , Keisuke Nakashima , Shigeru Matsuo , Masahisa Narita , Koyo Katsura , Hidehito Takewa , Tomoaki Aoki
IPC分类号： G06F1562
CPC分类号： G06T15/40 , G06T1/20
摘要： In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

69. 发明授权

US5526509A Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation 失效
公开(公告)号：US5526509A
公开(公告)日：1996-06-11
申请号：US386757
申请日：1995-02-10
申请人： Toshio Doi , Takeshi Takemoto , Yasuhiro Nakatsuka
发明人： Toshio Doi , Takeshi Takemoto , Yasuhiro Nakatsuka
IPC分类号： G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/0808 , G06F12/1063
摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

70. 发明授权

US5287465A Parallel processing apparatus and method capable of switching parallel and successive processing modes 失效
标题翻译：并行处理装置和方法能够切换并行和连续的处理模式
公开(公告)号：US5287465A
公开(公告)日：1994-02-15
申请号：US549916
申请日：1990-07-09
申请人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
发明人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
IPC分类号： G06F9/318 , G06F9/38 , G06F12/08 , G06F15/177 , G06F9/00
CPC分类号： G06F9/30189 , G06F9/30181 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed. Further, the parallel processing apparatus making great account of compatibility of a great part of software reads out m instructions without using the processing state flag, decodes the m instructions, checks whether a branch instruction exists in the k-th instruction, then executes the first to the (k+1)-th instructions in k+1 arithmetic units, and prevent execution of the (k+ 2)-th to m-th instructions. By executing the k-th branch instruction, the parallel processing apparatus calculates an address nm+h of its branch destination, performs calculation to check whether the condition is satisfied or not, then prevents execution of instructions of addresses nm to nm+h-1, and executes instructions of addresses nm+h to (n+1)m. In this way, the parallel processing apparatus executes a plurality of instructions and successively executes branch instructions.
摘要翻译：当执行常规软件的连续处理时，并行处理装置将处理状态判别标志关闭，一次将程序数增加1，读出一个指令，并在运算单元中处理该指令。当执行新软件的并行处理时，并行处理装置将处理状态判别转为一次，一次增加程序数m，读出m个指令，并对m个运算单元中的m个指令进行并行处理。为了选择上述两种处理之一，添加具有改变处理状态判别标志的功能的识别切换指令。指令根据处理状态判别标志在算术单元中进行处理。以这种方式，连续处理和并行处理具有兼容性并且被选择性地执行。此外，大量软件的兼容性的并行处理装置在不使用处理状态标志的情况下读出m个指令，对m个指令进行解码，检查第k个指令中是否存在转移指令，然后执行第一到第k + 1个算术单元中的第（k + 1）个指令，并且防止执行第（k + 2）至第m指令。通过执行第k个分支指令，并行处理装置计算其分支目的地的地址nm + h，执行计算以检查条件是否满足，然后防止执行地址nm到nm + h-1的指令并且执行地址nm + h至（n + 1）m的指令。以这种方式，并行处理装置执行多个指令，并连续执行分支指令。

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