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61. 发明授权

US06319730B1 Method of fabricating a semiconductor structure including a metal oxide interface 有权
标题翻译：制造包括金属氧化物界面的半导体结构的方法
公开(公告)号：US06319730B1
公开(公告)日：2001-11-20
申请号：US09354522
申请日：1999-07-15
申请人： Jamal Ramdani , Ravindranath Droopad , Zhiyi Yu
发明人： Jamal Ramdani , Ravindranath Droopad , Zhiyi Yu
IPC分类号： H01L2100
CPC分类号： H01L21/31691
摘要： A method for fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12); forming amorphous silicon dioxide (14) on the surface (12) of the silicon substrate (10); providing a metal oxide (18) on the amorphous silicon dioxide (14); heating the semiconductor structure to form an interface comprising a seed layer (20) adjacent the surface (12) of the silicon substrate (10); and forming one or more layers of a high dielectric constant oxide (22) on the seed layer (20).
摘要翻译：一种制造半导体结构的方法，包括以下步骤：提供具有表面（12）的硅衬底（10）; 在所述硅衬底（10）的表面（12）上形成无定形二氧化硅（14）; 在所述无定形二氧化硅（14）上提供金属氧化物（18）; 加热半导体结构以形成包括邻近硅衬底（10）的表面（12）的晶种层（20）的界面; 以及在种子层（20）上形成一层或多层高介电常数氧化物（22）。

62. 发明授权

US6160830A Semiconductor laser device and method of manufacture 失效
公开(公告)号：US6160830A
公开(公告)日：2000-12-12
申请号：US34279
申请日：1998-03-04
申请人： Philip Anthony Kiely , Paul Robert Claisse , Jamal Ramdani
发明人： Philip Anthony Kiely , Paul Robert Claisse , Jamal Ramdani
IPC分类号： H01S5/183 , H01S3/19
CPC分类号： H01S5/18308 , H01S5/18341 , H01S5/18369
摘要： A Vertical Cavity Surface Emitting Laser (VCSEL) (10) and a method for manufacturing the VCSEL (10). The VCSEL (10) includes a ridge structure (34), a first confinement layer (36) disposed adjacent to a portion of the ridge structure (34), and a second confinement layer (37) disposed on the first confinement layer (36) and disposed adjacent to a portion of the ridge structure (32). Carriers injected into the ridge structure (34) are confined by the first confinement layer (36).

63. 发明授权

US08624260B2 Enhancement-mode GaN MOSFET with low leakage current and improved reliability 有权
标题翻译：增强型GaN MOSFET具有低漏电流和可靠性
公开(公告)号：US08624260B2
公开(公告)日：2014-01-07
申请号：US12697235
申请日：2010-01-30
申请人： Jamal Ramdani
发明人： Jamal Ramdani
IPC分类号： H01L29/15
CPC分类号： H01L29/66431 , H01L21/02458 , H01L21/0254 , H01L21/28264 , H01L29/1054 , H01L29/2003 , H01L29/205 , H01L29/513 , H01L29/518 , H01L29/66462 , H01L29/66522 , H01L29/7787
摘要： An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.
摘要翻译：通过在AlGaN（或InAlGaN）阻挡层上利用SiO 2 / Si 3 N 4栅极绝缘层，形成具有低漏电流和提高的可靠性的增强型GaN MOSFET。 SiO 2 / Si 3 N 4栅极绝缘层的Si 3 N 4部分显着地减少了在栅极绝缘层和阻挡层之间的接合处的界面态的形成，而SiO 2 / Si 3 N 4栅极绝缘层的SiO 2部分显着降低了漏电流。

64. 发明授权

US08592292B2 Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates 有权
公开(公告)号：US08592292B2
公开(公告)日：2013-11-26
申请号：US12807336
申请日：2010-09-02
申请人： Sandeep R. Bahl , Jamal Ramdani
发明人： Sandeep R. Bahl , Jamal Ramdani
IPC分类号： H01L21/20
CPC分类号： H01L21/762 , H01L21/0237 , H01L21/02381 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/02639 , H01L21/7605 , H01L23/485 , H01L27/0605 , H01L27/088 , H01L29/0649 , H01L29/1075 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要： A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

65. 发明申请

US20110186855A1 Enhancement-Mode GaN MOSFET with Low Leakage Current and Improved Reliability 有权
标题翻译：具有低漏电流的增强型GaN MOSFET和改进的可靠性
公开(公告)号：US20110186855A1
公开(公告)日：2011-08-04
申请号：US12697235
申请日：2010-01-30
申请人： Jamal Ramdani
发明人： Jamal Ramdani
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/66431 , H01L21/02458 , H01L21/0254 , H01L21/28264 , H01L29/1054 , H01L29/2003 , H01L29/205 , H01L29/513 , H01L29/518 , H01L29/66462 , H01L29/66522 , H01L29/7787
摘要： An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.
摘要翻译：通过在AlGaN（或InAlGaN）阻挡层上利用SiO 2 / Si 3 N 4栅极绝缘层，形成具有低漏电流和提高的可靠性的增强型GaN MOSFET。 SiO 2 / Si 3 N 4栅极绝缘层的Si 3 N 4部分显着地减少了在栅极绝缘层和阻挡层之间的接合处的界面态的形成，而SiO 2 / Si 3 N 4栅极绝缘层的SiO 2部分显着降低了漏电流。

66. 发明申请

US20110140173A1 Low OHMIC contacts containing germanium for gallium nitride or other nitride-based power devices 审中-公开
标题翻译：用于氮化镓或其他基于氮化物的功率器件的含有锗的低OHMIC接触
公开(公告)号：US20110140173A1
公开(公告)日：2011-06-16
申请号：US12927948
申请日：2010-11-30
申请人： Jamal Ramdani
发明人： Jamal Ramdani
IPC分类号： H01L29/66 , H01L21/20
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/452 , H01L29/66462
摘要： An apparatus includes a substrate, a Group III-nitride layer over the substrate, and an electrical contact over the Group III-nitride layer. The electrical contact includes a stack having multiple layers of conductive material, and at least one of the layers in the stack includes germanium. The layers in the stack may include a contact layer, where the contact layer includes aluminum copper. The stack could include a titanium or titanium alloy layer, an aluminum or aluminum alloy layer, and a germanium or germanium alloy layer. At least one of the layers in the stack could include an aluminum or titanium alloy having a germanium content between about 1% and about 5%.
摘要翻译：一种装置包括衬底，衬底上的III族氮化物层，以及III族氮化物层上的电接触。电触点包括具有多层导电材料的叠层，堆叠中的至少一层包括锗。堆叠中的层可以包括接触层，其中接触层包括铝铜。叠层可以包括钛或钛合金层，铝或铝合金层以及锗或锗合金层。堆叠中的至少一个层可以包括锗含量在约1％和约5％之间的铝或钛合金。

67. 发明申请

US20110140118A1 Backside stress compensation for gallium nitride or other nitride-based semiconductor devices 有权
标题翻译：氮化镓或其他氮化物基半导体器件的背面应力补偿
公开(公告)号：US20110140118A1
公开(公告)日：2011-06-16
申请号：US12927931
申请日：2010-11-30
申请人： Jamal Ramdani
发明人： Jamal Ramdani
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L21/02667 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02592 , H01L21/02595 , H01L21/02658 , H01L29/2003 , H01L29/7787
摘要： A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate.
摘要翻译：一种方法包括在半导体衬底的第一侧上形成应力补偿层，并在衬底的第二面上形成III族氮化物层。通过III族氮化物层在衬底上产生的应力通过应力补偿层在衬底上产生的应力至少部分地减小。形成应力补偿层可以包括从非晶或微晶材料形成应力补偿层。此外，该方法可以包括在随后在衬底的第二侧上形成一层或多层之后使无定形或微晶材料结晶。在随后形成III族氮化物层和/或退火过程期间，可能发生非晶或微晶材料的结晶。无定形或微晶材料在基底上不会产生或少量的应力，并且结晶的材料可能在基底上产生更大量的应力。

68. 发明授权

US07892915B1 High performance SiGe:C HBT with phosphorous atomic layer doping 有权
标题翻译：高性能SiGe：C HBT具有磷原子层掺杂
公开(公告)号：US07892915B1
公开(公告)日：2011-02-22
申请号：US11367030
申请日：2006-03-02
申请人： Jamal Ramdani , Craig Richard Printy , Thanas Budri
发明人： Jamal Ramdani , Craig Richard Printy , Thanas Budri
IPC分类号： H01L21/8249
CPC分类号： H01L29/7378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/02617
摘要： A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosophorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles.
摘要翻译：公开了一种用于高性能硅锗：具有磷光原子层掺杂（ALD）的碳（SiGe：C）基异质结双极晶体管（HBT））的基本结构。 ALD工艺使基底衬底受氮气（在大约等于500摄氏度的环境温度下），并提供另外的SiGe：C间隔层。在ALD过程中，锗（Ge）和碳（C）的百分比浓度基本匹配，磷是优选的掺杂剂。改进的SiGe：C HBT对工艺温度和曝光时间较不敏感，并且显示较低的掺杂剂偏析和更尖锐的基体分布。

69. 发明授权

US07687887B1 Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter 有权
标题翻译：使用选择性生长的发射极形成自对准双极晶体管结构的方法
公开(公告)号：US07687887B1
公开(公告)日：2010-03-30
申请号：US11607265
申请日：2006-12-01
申请人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
发明人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
IPC分类号： H01L21/00
CPC分类号： H01L29/0817 , H01L29/66242 , H01L29/7378
摘要： A method for forming a self-aligned bipolar transistor structure uses the selective growth of a doped silicon emitter in a sloped oxide emitter window to form the self-aligned structure. In an alternate process flow, the top emitter layer is SiGe with a high Ge content that is etched off selectively after deposition of the extrinsic base layer. In another alternate flow, a nitride plug formed on top of the emitter blocks the extrinsic base implant from the emitter region.
摘要翻译：用于形成自对准双极晶体管结构的方法使用在倾斜的氧化物发射器窗口中的掺杂硅发射体的选择性生长以形成自对准结构。在替代工艺流程中，顶部发射极层是具有高Ge含量的SiGe，其在沉积外部基极层之后被选择性地蚀刻掉。在另一个替代流程中，形成在发射极顶部的氮化物塞从发射极区域阻挡外部基极注入。

70. 发明授权

US06555946B1 Acoustic wave device and process for forming the same 失效
标题翻译：声波装置及其形成方法
公开(公告)号：US06555946B1
公开(公告)日：2003-04-29
申请号：US09624803
申请日：2000-07-24
申请人： Jeffrey M. Finder , Kurt Eisenbeiser , Jamal Ramdani , Ravindranath Droopad , William Jay Ooms
发明人： Jeffrey M. Finder , Kurt Eisenbeiser , Jamal Ramdani , Ravindranath Droopad , William Jay Ooms
IPC分类号： H01L4108
CPC分类号： H03H9/174 , H01L27/20 , H01L41/319 , H03H3/02 , H03H3/08 , H03H9/02574 , H03H9/0542
摘要： High quality epitaxial layers of piezoelectric material materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
摘要翻译：通过首先在硅晶片上生长一个容纳缓冲层，可以将高质量的压电材料外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

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