专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08148799B2 Self-aligned bipolar transistor structure 有权
标题翻译：自对准双极晶体管结构
公开(公告)号：US08148799B2
公开(公告)日：2012-04-03
申请号：US12692892
申请日：2010-01-25
申请人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
发明人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
IPC分类号： H01L21/00
CPC分类号： H01L29/0817 , H01L29/66242 , H01L29/7378
摘要： A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.
摘要翻译：双极晶体管结构包括具有第一导电类型的半导体衬底，具有与在形成于半导体衬底的上表面中的隔离电介质材料限定的衬底有源器件区域中形成的第一导电类型相反的第二导电类型的集电极区域包括在集电极区域上形成的具有第一导电类型的本征基极区域和形成在隔离电介质材料上的具有第二导电类型的非本征基极区域的基极区域和具有第二导电性的倾斜的原位掺杂发射极插塞形成在本征基区上。

2. 发明授权

US5846866A Drain extension regions in low voltage lateral DMOS devices 失效
标题翻译：在低压横向DMOS器件中漏极延伸区域
公开(公告)号：US5846866A
公开(公告)日：1998-12-08
申请号：US897278
申请日：1997-07-21
申请人： Robert Y. S. Huang , Monir El-Diwany
发明人： Robert Y. S. Huang , Monir El-Diwany
IPC分类号： H01L29/08 , H01L29/78 , H01L21/8224
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/7801
摘要： Disclosed are MOSFET devices in which a region extends from the drain and is, self-aligned with the gate. The region has a lower dopant concentration than the drain. The presence of the extension region substantially enhances breakdown voltage while not adding excessive on-resistance for the devices.
摘要翻译：公开了一种MOSFET器件，其中区域从漏极延伸并且与栅极自对准。该区域的掺杂浓度低于漏极。扩展区域的存在基本上增强了击穿电压，同时不会对器件增加过多的导通电阻。

3. 发明授权

US5766990A Method of manufacturing a high speed bipolar transistor in a CMOS process 失效
标题翻译：在CMOS工艺中制造高速双极晶体管的方法
公开(公告)号：US5766990A
公开(公告)日：1998-06-16
申请号：US907874
申请日：1997-08-11
申请人： Monir El-Diwany
发明人： Monir El-Diwany
IPC分类号： H01L21/8249 , H01L27/06 , H01L21/8238
CPC分类号： H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Fabrication of a high frequency bipolar transistor structure is integrated into a CMOS process flow with minimal additional cost. The polysilicon emitter of the bipolar device and the polysilicon gate of the MOS device use separate polysilicon layers and, therefore, allow the bipolar emitter and the MOS gate to be doped independently of each other. The process scheme does not require the MOS device to be subdivided.
摘要翻译：将高频双极晶体管结构的制造集成到CMOS工艺流程中，同时具有最小的附加成本。双极器件的多晶硅发射极和MOS器件的多晶硅栅极使用分离的多晶硅层，因此允许双极发射极和MOS栅极彼此独立地掺杂。处理方案不需要将MOS器件细分。

4. 发明授权

US5953599A Method for forming low-voltage CMOS transistors with a thin layer of gate oxide and high-voltage CMOS transistors with a thick layer of gate oxide 失效
标题翻译：用栅极氧化物的薄层形成低压CMOS晶体管的方法和具有厚层栅极氧化物的高压CMOS晶体管
公开(公告)号：US5953599A
公开(公告)日：1999-09-14
申请号：US873822
申请日：1997-06-12
申请人： Monir El-Diwany
发明人： Monir El-Diwany
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/8238
摘要： The low-voltage, e.g., 2.5-volt, transistors that support the logic operations of a CMOS device are formed to have a thin layer of gate oxide, while the high-voltage, e.g., 3.3 or 5-volt, transistors that support the analog operations of the device are formed to have a thick layer of gate oxide in a cost-effective process flow that requires only one additional masking step over a conventional double-poly CMOS process.
摘要翻译：支持CMOS器件的逻辑操作的低电压（例如2.5伏）晶体管形成为具有薄层的栅极氧化物，而高电压（例如3.3或5伏）的晶体管支持在成本有效的工艺流程中，器件的模拟操作形成为具有厚的栅极氧化层，其在传统的双聚CMOS工艺中仅需要一个附加的掩模步骤。

5. 发明申请

US20100127352A1 SELF-ALIGNED BIPOLAR TRANSISTOR STRUCTURE 有权
标题翻译：自对准双极晶体管结构
公开(公告)号：US20100127352A1
公开(公告)日：2010-05-27
申请号：US12692892
申请日：2010-01-25
申请人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
发明人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
IPC分类号： H01L29/732 , H01L29/73
CPC分类号： H01L29/0817 , H01L29/66242 , H01L29/7378
摘要： A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.
摘要翻译：双极晶体管结构包括具有第一导电类型的半导体衬底，具有与在形成于半导体衬底的上表面中的隔离电介质材料限定的衬底有源器件区域中形成的第一导电类型相反的第二导电类型的集电极区域包括在集电极区域上形成的具有第一导电类型的本征基极区域和形成在隔离电介质材料上的具有第二导电类型的非本征基极区域的基极区域和具有第二导电性的倾斜的原位掺杂发射极插塞形成在本征基区上。

6. 发明授权

US07687887B1 Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter 有权
标题翻译：使用选择性生长的发射极形成自对准双极晶体管结构的方法
公开(公告)号：US07687887B1
公开(公告)日：2010-03-30
申请号：US11607265
申请日：2006-12-01
申请人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
发明人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
IPC分类号： H01L21/00
CPC分类号： H01L29/0817 , H01L29/66242 , H01L29/7378
摘要： A method for forming a self-aligned bipolar transistor structure uses the selective growth of a doped silicon emitter in a sloped oxide emitter window to form the self-aligned structure. In an alternate process flow, the top emitter layer is SiGe with a high Ge content that is etched off selectively after deposition of the extrinsic base layer. In another alternate flow, a nitride plug formed on top of the emitter blocks the extrinsic base implant from the emitter region.
摘要翻译：用于形成自对准双极晶体管结构的方法使用在倾斜的氧化物发射器窗口中的掺杂硅发射体的选择性生长以形成自对准结构。在替代工艺流程中，顶部发射极层是具有高Ge含量的SiGe，其在沉积外部基极层之后被选择性地蚀刻掉。在另一个替代流程中，形成在发射极顶部的氮化物塞从发射极区域阻挡外部基极注入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式