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1. 发明授权

US07892915B1 High performance SiGe:C HBT with phosphorous atomic layer doping 有权
标题翻译：高性能SiGe：C HBT具有磷原子层掺杂
公开(公告)号：US07892915B1
公开(公告)日：2011-02-22
申请号：US11367030
申请日：2006-03-02
申请人： Jamal Ramdani , Craig Richard Printy , Thanas Budri
发明人： Jamal Ramdani , Craig Richard Printy , Thanas Budri
IPC分类号： H01L21/8249
CPC分类号： H01L29/7378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/02617
摘要： A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosophorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles.
摘要翻译：公开了一种用于高性能硅锗：具有磷光原子层掺杂（ALD）的碳（SiGe：C）基异质结双极晶体管（HBT））的基本结构。 ALD工艺使基底衬底受氮气（在大约等于500摄氏度的环境温度下），并提供另外的SiGe：C间隔层。在ALD过程中，锗（Ge）和碳（C）的百分比浓度基本匹配，磷是优选的掺杂剂。改进的SiGe：C HBT对工艺温度和曝光时间较不敏感，并且显示较低的掺杂剂偏析和更尖锐的基体分布。

2. 发明申请

US20100276740A1 Method for fabricating higher quality thicker gate oxide in a non-volatile memory cell and associated circuits 有权
公开(公告)号：US20100276740A1
公开(公告)日：2010-11-04
申请号：US12803989
申请日：2010-07-12
申请人： Thanas Budri , Jiankang Bu
发明人： Thanas Budri , Jiankang Bu
IPC分类号： H01L27/115 , H01L27/06
CPC分类号： H01L21/823892 , H01L21/823857 , H01L27/11526 , H01L27/11546 , Y10S438/981
摘要： A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.

3. 发明授权

US08481142B1 System and method for monitoring chloride content and concentration induced by a metal etch process 有权
标题翻译：用于监测由金属蚀刻工艺引起的氯化物含量和浓度的系统和方法
公开(公告)号：US08481142B1
公开(公告)日：2013-07-09
申请号：US11215845
申请日：2005-08-30
申请人： Thanas Budri , Thomas Francis , David Tucker , Stephen W. Swan , Sergei Drizlikh
发明人： Thanas Budri , Thomas Francis , David Tucker , Stephen W. Swan , Sergei Drizlikh
IPC分类号： H01L21/302
CPC分类号： G01N23/223 , G01N2223/076 , H01L21/32136 , H01L22/12 , Y10T428/234
摘要： A system and method for monitoring chloride content and concentration induced by a metal etch process is disclosed. A blank metal film is deposited on a semiconductor wafer. A metal etch process is then applied to partially etch the blank metal film on the wafer. The metal etch process exposes the metal film to chlorine. The wafer is then scanned using surface profiling total X-ray reflection fluorescence. A chlorine concentration map is generated that shows quantitative and spatial information about the chlorine on the wafer. Information from the chlorine concentration map is then used to select a value of chlorine concentration for a metal etch process that will not create metal chloride corrosion on a semiconductor wafer.
摘要翻译：公开了一种用于监测由金属蚀刻工艺引起的氯化物含量和浓度的系统和方法。空白金属膜沉积在半导体晶片上。然后施加金属蚀刻工艺以部分地蚀刻晶片上的空白金属膜。金属蚀刻工艺将金属膜暴露于氯。然后使用表面形貌总X射线反射荧光扫描晶片。产生氯浓度图，其显示关于晶片上的氯的定量和空间信息。然后使用来自氯浓度图的信息来选择不会在半导体晶片上产生金属氯化物腐蚀的金属蚀刻工艺的氯浓度值。

4. 发明授权

US08115196B2 High performance SiGe:C HBT with phosphorous atomic layer doping 有权
标题翻译：高性能SiGe：C HBT具有磷原子层掺杂
公开(公告)号：US08115196B2
公开(公告)日：2012-02-14
申请号：US13031496
申请日：2011-02-21
申请人： Janial Ramdani , Craig Richard Printy , Thanas Budri
发明人： Janial Ramdani , Craig Richard Printy , Thanas Budri
IPC分类号： H01L31/00
CPC分类号： H01L29/7378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/02617
摘要： A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosphorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles.
摘要翻译：公开了具有磷原子层掺杂（ALD）的高性能硅锗：基于碳（SiGe：C）的异质结双极晶体管（HBT）的基础结构。 ALD工艺使基底衬底受氮气（在大约等于500摄氏度的环境温度下），并提供另外的SiGe：C间隔层。在ALD过程中，锗（Ge）和碳（C）的百分比浓度基本匹配，磷是优选的掺杂剂。改进的SiGe：C HBT对工艺温度和曝光时间较不敏感，并且显示较低的掺杂剂偏析和更尖锐的基体分布。

5. 发明授权

US08097923B2 Method for fabricating higher quality thicker gate oxide in a non-volatile memory cell and associated circuits 有权
标题翻译：在非易失性存储单元和相关电路中制造较高质量较厚栅极氧化物的方法
公开(公告)号：US08097923B2
公开(公告)日：2012-01-17
申请号：US12803989
申请日：2010-07-12
申请人： Thanas Budri , Jiankang Bu
发明人： Thanas Budri , Jiankang Bu
IPC分类号： H01L27/088
CPC分类号： H01L21/823892 , H01L21/823857 , H01L27/11526 , H01L27/11546 , Y10S438/981
摘要： A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.
摘要翻译：非易失性存储单元包括程序晶体管和控制电容器。与程序晶体管相关联的衬底的一部分暴露于多次注入（例如DNW，HiNWell，HiPWell和P阱注入）。类似地，与控制电容器相关联的衬底的一部分暴露于多次注入（例如DNW，HiNWell，HiPWell，P阱和N阱注入）。衬底的这些部分可以具有比衬底的其它部分更快的氧化速率，允许在衬底的这些部分上形成较厚的前端栅极氧化物。此外，可以进行快速热处理退火，这可以减少前端栅极氧化物中的缺陷并提高其质量，而不会对衬底的其它部分上的氧化物产生太大影响。

6. 发明授权

US07319530B1 System and method for measuring germanium concentration for manufacturing control of BiCMOS films 有权
标题翻译：用于测量BiCMOS膜制造控制的锗浓度的系统和方法
公开(公告)号：US07319530B1
公开(公告)日：2008-01-15
申请号：US10811738
申请日：2004-03-29
申请人： Craig Printy , Thanas Budri
发明人： Craig Printy , Thanas Budri
IPC分类号： G01B11/28 , H01L21/66
CPC分类号： G01B11/065 , G01N21/211 , G01N21/8422 , G01N2021/213 , H01L22/12
摘要： A system and method is disclosed for measuring a germanium concentration in a semiconductor wafer for manufacturing control of BiCMOS films. Germanium is deposited over a silicon substrate layer to form a silicon germanium film. Then a rapid thermal oxidation (RTO) procedure is performed to create a layer of thermal oxide over the silicon germanium film. The thickness of the layer of thermal oxide is measured in real time using an interferometer, an ellipsometer, or a spectroscopic ellipsometer. The measured thickness of the layer of thermal oxide is correlated to a germanium concentration of the silicon germanium film using an approximately linear correlation. The correlation enables a value of the germanium concentration in the silicon germanium film to be provided in real time.
摘要翻译：公开了一种用于测量用于制造BiCMOS膜的控制的半导体晶片中的锗浓度的系统和方法。锗沉积在硅衬底层上以形成硅锗膜。然后进行快速热氧化（RTO）程序，以在硅锗膜上形成一层热氧化物。使用干涉仪，椭偏仪或光谱椭偏仪实时测量热氧化物层的厚度。热氧化物层的测量厚度与硅锗膜的锗浓度相关，使用近似线性相关。相关性能够实时提供硅锗膜中的锗浓度的值。

7. 发明授权

US07038222B1 System and method for using areas near photo global alignment marks or unpatterned areas of a semiconductor wafer to create structures for SIMS or E-Beam or XRD testing 有权
标题翻译：使用半导体晶片的照片全局对准标记或未图案化区域附近的区域的系统和方法来创建SIMS或E-Beam或XRD测试的结构
公开(公告)号：US07038222B1
公开(公告)日：2006-05-02
申请号：US10869681
申请日：2004-06-16
申请人： Thanas Budri , Aaron Michael Smith , Neil Suresh Patel , Loren Charles Krott
发明人： Thanas Budri , Aaron Michael Smith , Neil Suresh Patel , Loren Charles Krott
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/34 , G01N23/20 , G01N23/22
摘要： A system and method is described for using areas in or near photo global alignment marks or in or near unpatterned areas of a semiconductor wafer to create structures for secondary ion mass spectroscopy (SIMS) testing or electron beam (E-Beam) testing or X-ray diffraction (XRD) testing of the semiconductor wafer. The present invention makes it possible to obtain wafer level information about the front-end processing of the semiconductor wafers. The SIMS/E-Beam/XRD testing measures characteristics such as the dopant content, thickness variations, and defect density of the wafers. The present invention eliminates the need to build individual test structures within product dies and eliminates the need to build scribe line structures near the product dies.
摘要翻译：描述了一种系统和方法，用于使用光全局对准标记内或附近的区域，或在半导体晶片的未图案化区域或其附近，以产生用于二次离子质谱（SIMS）测试或电子束（E-Beam）测试或X- 半导体晶片的X射线衍射（XRD）测试。本发明可以获得关于半导体晶片的前端处理的晶片级信息。 SIMS / E-beam / XRD测试测量诸如晶片的掺杂剂含量，厚度变化和缺陷密度的特征。本发明消除了在产品模具内构建单个测试结构的需要，并且消除了在产品模具附近构建划线结构的需要。

8. 发明授权

US08679936B1 Manufacturing resistors with tightened resistivity distribution in semiconductor integrated circuits 有权
标题翻译：制造电阻器在半导体集成电路中具有紧密的电阻率分布
公开(公告)号：US08679936B1
公开(公告)日：2014-03-25
申请号：US11138031
申请日：2005-05-26
申请人： Thanas Budri , Jerald M. Rock , Randy Supczak
发明人： Thanas Budri , Jerald M. Rock , Randy Supczak
IPC分类号： H01L21/20
CPC分类号： H01L29/8605 , H01L21/26513 , H01L21/324
摘要： An anneal recipe is provided to tighten the distribution of resistance values in the manufacture of semiconductor integrated circuits. An adjusted amount of dopant is implanted to compensate for a shift in the distribution of resistance values associated with the anneal recipe. The distribution tightening can be effectuated by including an ammonia gas flow in the anneal recipe.
摘要翻译：提供退火配方以在半导体集成电路的制造中紧固电阻值的分布。植入调整量的掺杂剂以补偿与退火配方相关联的电阻值分布的偏移。分配紧固可以通过在退火配方中包括氨气流来实现。

9. 发明申请

US20110180848A1 HIGH PERFORMANCE SiGe:C HBT WITH PHOSPHOROUS ATOMIC LAYER DOPING 有权
标题翻译：高性能SiGe：C HBT与磷光体原子层掺杂
公开(公告)号：US20110180848A1
公开(公告)日：2011-07-28
申请号：US13031496
申请日：2011-02-21
申请人： Jamal Ramdani , Craig Richard Printy , Thanas Budri
发明人： Jamal Ramdani , Craig Richard Printy , Thanas Budri
IPC分类号： H01L29/06
CPC分类号： H01L29/7378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/02617
摘要： A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosphorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles.
摘要翻译：公开了具有磷原子层掺杂（ALD）的高性能硅锗：基于碳（SiGe：C）的异质结双极晶体管（HBT）的基础结构。 ALD工艺使基底衬底受氮气（在大约等于500摄氏度的环境温度下），并提供另外的SiGe：C间隔层。在ALD过程中，锗（Ge）和碳（C）的百分比浓度基本匹配，磷是优选的掺杂剂。改进的SiGe：C HBT对工艺温度和曝光时间较不敏感，并且显示较低的掺杂剂偏析和更尖锐的基体分布。

10. 发明授权

US07781289B1 Method for fabricating higher quality thicker gate oxide in a non-volatile memory cell and associated circuits 有权
标题翻译：在非易失性存储单元和相关电路中制造较高质量较厚栅极氧化物的方法
公开(公告)号：US07781289B1
公开(公告)日：2010-08-24
申请号：US11799921
申请日：2007-05-03
申请人： Thanas Budri , Jiankang Bu
发明人： Thanas Budri , Jiankang Bu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823892 , H01L21/823857 , H01L27/11526 , H01L27/11546 , Y10S438/981
摘要： A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.
摘要翻译：非易失性存储单元包括程序晶体管和控制电容器。与程序晶体管相关联的衬底的一部分暴露于多次注入（例如DNW，HiNWell，HiPWell和P阱注入）。类似地，与控制电容器相关联的衬底的一部分暴露于多次注入（例如DNW，HiNWell，HiPWell，P阱和N阱注入）。衬底的这些部分可以具有比衬底的其它部分更快的氧化速率，允许在衬底的这些部分上形成较厚的前端栅极氧化物。此外，可以进行快速热处理退火，这可以减少前端栅极氧化物中的缺陷并提高其质量，而不会对衬底的其它部分上的氧化物产生太大影响。

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