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61. 发明授权

US06258668B1 Array architecture and process flow of nonvolatile memory devices for mass storage applications 有权
标题翻译：用于大容量存储应用的非易失性存储器件的阵列架构和处理流程
公开(公告)号：US06258668B1
公开(公告)日：2001-07-10
申请号：US09487501
申请日：2000-01-19
申请人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
发明人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0491 , H01L27/115
摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.
摘要翻译：在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。

62. 发明授权

US5882123A Roll-formed bearing race and process for producing the same 失效
标题翻译：滚动轴承种类及其制造方法
公开(公告)号：US5882123A
公开(公告)日：1999-03-16
申请号：US868457
申请日：1997-06-03
申请人： Peter W. Lee , Martin D. Pierce , Goverdhan D. Lahoti
发明人： Peter W. Lee , Martin D. Pierce , Goverdhan D. Lahoti
IPC分类号： B21D53/10 , B21H1/12 , F16C19/38 , F16C33/60 , F16C33/64 , B21D17/04 , B21H1/06
CPC分类号： F16C19/386 , B21H1/12 , F16C33/60 , F16C33/64 , Y10T29/49689
摘要： A double cup for a tapered roller being has a concave intervening surface between the small diameter ends of its tapered raceways. The cup is produced by roll forming a tubular blank at ambient temperature into a ring form having the raceways and the concave intervening surface. The presence of the concave intervening surface leaves only a shallow discontinuity in the exterior surface of the ring form, and that discontinuity is machined away with the removal of only a minimal amount of stock. The cup weighs less than cups with straight intervening surfaces.
摘要翻译：圆锥滚子的双杯在其锥形滚道的小直径端之间具有凹入的中间表面。通过在环境温度下将管状坯料卷成成具有滚道和凹入中间表面的环形来制造杯子。凹形中间表面的存在仅在环形表面的外表面中仅留下浅的不连续性，并且通过仅去除最少量的原料来加工不连续性。杯子重量小于具有直的中间表面的杯子。

63. 发明授权

US5848000A Flash memory address decoder with novel latch structure 失效
标题翻译：具有新型锁存结构的闪存地址解码器
公开(公告)号：US5848000A
公开(公告)日：1998-12-08
申请号：US819323
申请日：1997-03-18
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/10 , G11C8/12 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/3418 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3413 , G11C16/3431 , G11C8/10 , G11C8/12 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2216/20 , G11C7/18 , G11C8/00
摘要： A flash memory address decoder includes a plurality of voltage terminals to receive a plurality of voltages, an address terminal to receive a plurality of address signals and a procedure terminal to receive a procedure signal. A block decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a block select signal. A wordline decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a wordline select signal. A wordline selector circuit is coupled to the block decoder and the wordline decoder and configured to receive the block select signal and the wordline select signal and to activate addressed wordlines, where the wordline selector is configured to selectively activate addressed wordlines in the flash transistor array and to provide at least two different operational voltages simultaneously on different wordlines in the flash transistor array to accomplish a predetermined procedure responsive to the procedure signal. In one embodiment, a the address decoder includes a latch structure that latches addressed wordlines and provides operational voltages to the wordlines. In another embodiment, the block decoder and wordline decoder include latch structures that latch the block select signal and the wordline select signal to provide operational voltages to the wordline selector. Advantages of the invention include high accuracy and flexibility to read, erase and program the flash memory.
摘要翻译：闪存地址解码器包括多个用于接收多个电压的电压端子，用于接收多个地址信号的地址端子和用于接收过程信号的过程终端。块解码器耦合到地址终端并且被配置为对部分地址信号进行解码以提供块选择信号。字线解码器耦合到地址终端，并且被配置为对地址信号的一部分进行解码以提供字线选择信号。字线选择器电路耦合到块解码器和字线解码器并且被配置为接收块选择信号和字线选择信号并激活寻址字线，其中字线选择器被配置为选择性地激活闪存晶体管阵列中的寻址字线，以在闪光晶体管阵列中的不同字线上同时提供至少两个不同的操作电压，以响应于过程信号来完成预定的过程。在一个实施例中，地址解码器包括锁存寻址字线并向字线提供工作电压的锁存结构。在另一个实施例中，块解码器和字线解码器包括锁存块选择信号和字线选择信号以向字线选择器提供工作电压的锁存结构。本发明的优点包括读取，擦除和编程闪存的高精度和灵活性。

64. 发明授权

US5822252A Flash memory wordline decoder with overerase repair 失效
标题翻译：闪存字幕解码器，过度修复
公开(公告)号：US5822252A
公开(公告)日：1998-10-13
申请号：US676066
申请日：1996-07-05
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3413 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/08 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： The invention provides a flash memory and decoder with overerase repair that can provide three word line voltages to overcome the overerased problems. The wordline decoder includes a wordline latch that provides a high flexibility of erasing size so that single/multiple sub-wordlines, single/multiple wordlines, single/multiple block, and whole array can be erased simultaneously. An exemplary embodiment of a flash memory wordline decoder that can provide three voltages includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes a plurality of latches coupled to the wordlines and configured to latch the wordlines and to provide one of a plurality of operational voltages on the wordlines to accomplish a predetermined operation responsive to the procedure signal. The plurality of voltage terminals are configured in a way that the high voltage required for erasure or for programming needs not be discharged in verification. Another exemplary embodiment provides a wordline decoder that provides three wordline voltages for verification and repairing, and also for erasure. Advantages of the invention include available full verifications for erasure, repairing and programming, tight cell threshold distribution, high efficiency repairing, no discharging the high voltage cells in verifications, full range verification voltages.
摘要翻译：本发明提供了具有过度修复的闪存和解码器，其可以提供三个字线电压以克服过度存在的问题。字线解码器包括字线锁存器，其提供擦除大小的高灵活性，使得可以同时擦除单个/多个子字线，单个/多个字线，单个/多个块和整个阵列。可以提供三个电压的闪存字线解码器的示例性实施例包括多个用于接收多个电压的电压端子，多个地址端子以接收多个地址信号，接收过程信号的过程终端，以及适于耦合到一组闪存晶体管的多个输出字线。字线解码器电路被配置为对地址信号进行解码，并且包括耦合到字线的多个锁存器，并被配置为锁存字线并且在字线上提供多个工作电压中的一个，以响应于过程信号来完成预定的操作。多个电压端子被配置为在验证中不需要消除擦除或编程所需的高电压。另一示例性实施例提供一种字线解码器，其提供用于验证和修复的三个字线电压，并且还用于擦除。本发明的优点包括用于擦除，修复和编程的可用的完整验证，紧密的单元阈值分布，高效率修复，在验证中不排放高电压单元，全范围验证电压。

65. 发明授权

US5572462A Multistate prom and decompressor 失效
标题翻译：多状态和解压缩器
公开(公告)号：US5572462A
公开(公告)日：1996-11-05
申请号：US510259
申请日：1995-08-02
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： G11C11/56
CPC分类号： G11C11/5692 , G11C11/56 , G11C7/1006
摘要： A multistate PROM and decompressor comprises a PROM array including a plurality of cells arranged to have a plurality of wordlines and a plurality of bitlines, where each cell is configured to have one of a plurality of threshold voltages (Vt0-Vtn). A Vt-detector is coupled to the PROM array and configured to receive a high voltage wordline (WLHV) signal that is ramped from a first voltage (e.g. 0V or ground) to a second voltage (e.g. Vtmax). The Vt-detector is configured to compare the WLHV signal to a plurality of predetermined thresholds and to output a detector word in response to the WLHV signal. An addressed memory cell is selected by a wordline select signal and a bitline select signal. A wordline selector is coupled to the PROM array and configured to receive the WLHV signal. The wordline selector communicates the WLHV signal to a selected wordline in response to the wordline select signal. A bitline selector is coupled to the PROM array and configured to select a selected bitline carrying a bitline signal in response to the bitline select signal. A decompressor is coupled to the Vt-detector and the bitline selector and is configured to receive the detector word and the bitline signal. When the WLHV signal voltage meets the addressed cell's voltage threshold, the addressed memory cell is turned on and the selected bitline signal is activated. Then, the detector word is latched into the decompressor and the data stored in the addressed memory cell is delivered to an output terminal. The first embodiment can be combined with a pump generator. A pump generator delivers a relatively high voltage to the WLHV signal input in order to permit a greater expanse among the operational voltage or current levels. This feature increases the range over which the selectable voltages operate. An advantage of this approach is that there is a greater chance of correct interpretation by the Vt-detector and decompressor.
摘要翻译：多状态PROM和解压缩器包括PROM阵列，其包括被布置为具有多个字线和多个位线的多个单元，其中每个单元被配置为具有多个阈值电压（Vt0-Vtn）中的一个。 Vt检测器耦合到PROM阵列并且被配置为接收从第一电压（例如0V或接地）斜坡到第二电压（例如Vtmax）的高电压字线（WLHV）信号。 Vt检测器被配置为将WLHV信号与多个预定阈值进行比较，并且响应于WLHV信号输出检测器字。寻址的存储单元由字线选择信号和位线选择信号选择。字线选择器耦合到PROM阵列并被配置为接收WLHV信号。字线选择器响应于字线选择信号将WLHV信号传送到所选择的字线。位线选择器耦合到PROM阵列并且被配置为响应于位线选择信号来选择携带位线信号的选定位线。解压缩器耦合到Vt检测器和位线选择器，并被配置为接收检测器字和位线信号。当WLHV信号电压满足寻址单元的电压阈值时，寻址的存储单元导通，并且所选择的位线信号被激活。然后，检测器字被锁存到解压缩器中，并且存储在寻址的存储单元中的数据被传送到输出端。第一实施例可以与泵发生器组合。泵发生器向WLHV信号输入端提供相对高的电压，以便允许在工作电压或电流水平之间更大的扩展。该功能增加了可选电压工作的范围。这种方法的一个优点是Vt检测器和解压缩器有更正确的解释机会。

66. 发明授权

US5314845A Two step process for forming void-free oxide layer over stepped surface of semiconductor wafer 失效
标题翻译：用于在半导体晶片的台阶表面上形成无空隙的氧化物层的两步法
公开(公告)号：US5314845A
公开(公告)日：1994-05-24
申请号：US474177
申请日：1990-02-02
申请人： Peter W. Lee , David N. Wang , Makoto Nagashima , Kazuto Fukuma , Tatsuya Sato
发明人： Peter W. Lee , David N. Wang , Makoto Nagashima , Kazuto Fukuma , Tatsuya Sato
IPC分类号： C23C16/40 , H01L21/316 , H01L21/768 , H01L23/29 , H01L23/31 , H01L23/532 , H01L21/00 , H01L21/02 , H01L21/302 , H01L21/463
CPC分类号： H01L21/02129 , C23C16/401 , C23C16/402 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02343 , H01L21/31612 , H01L21/31625 , H01L21/76819 , H01L23/291 , H01L23/3171 , H01L23/5329 , H01L2924/0002
摘要： A two step process is disclosed for forming a silicon oxide layer over a stepped surface of a semiconductor wafer while inhibiting the formation of voids in the oxide layer which comprises depositing a layer of an oxide of silicon over a stepped surface of a semiconductor wafer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3, and tetraethylorthosilicate as the gaseous source of silicon while maintaining the pressure in the CVD chamber within a range of from about 250 Torr to about 760 Torr and then depositing a second layer of oxide over the first layer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3 ; and tetraethylorthosilicate as the gaseous source of silicon while maintaining the CVD chamber at a lower pressure than during the first deposition step.
摘要翻译：公开了一种用于在半导体晶片的阶梯表面上形成氧化硅层的两步法，同时抑制氧化物层中的空隙的形成，其包括在半导体晶片的台阶表面上沉积硅的氧化物层 CVD室通过将包含氧源的气体混合物（其一部分包含O 3）和原硅酸四乙酯作为气态硅流入气室，同时将CVD室中的压力保持在约250托至约760的范围内然后通过流入室中在CVD室中的第一层上沉积第二层氧化物，气体混合物包含氧源，其一部分包含O 3; 和原硅酸四乙酯作为气态硅源，同时将CVD室保持在比在第一沉积步骤期间更低的压力。

67. 发明授权

US5309639A Method of making a machine component with lubricated wear surface 失效
标题翻译：制造具有润滑磨损表面的机器部件的方法
公开(公告)号：US5309639A
公开(公告)日：1994-05-10
申请号：US979902
申请日：1992-11-23
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： B22F3/11 , B22F3/24 , B23H9/00 , B23P13/04 , F16C33/60 , F16C33/66 , B23P13/02 , F16C33/64
CPC分类号： F16C33/6648 , B22F3/1103 , B22F3/24 , B23H9/008 , B23P13/04 , F16C19/364 , F16C33/605 , Y10S384/902 , Y10T29/49639 , Y10T29/49689 , Y10T29/49702 , Y10T29/49707 , Y10T29/49996
摘要： A machine component has a wear surface along which excessive friction will develop unless the surface receives adequate lubrication. To provide lubrication for the wear surface in the absence of any other lubricating medium, the component is formed from powdered metal compacted to less than theoretical density so as to contain pores, and the pores hold oil. Even though the component is mechanically machined along its wear surface, the pores are nevertheless open at the wear surface to enable the entrapped oil to exude from the ring and lubricate that surface. During manufacture of the ring, the mechanical machining creates a Bielby layer at the wear surface, that is it smears the metal and closes the pores at that surface, but the Bielby layer is removed by electro-discharge machining This procedure erodes the Bielby layer with electrical arcs so that the pores at the wear surface are again exposed and open.
摘要翻译：机器部件具有磨损表面，除非表面受到足够的润滑，否则磨损表面将产生过大的摩擦。为了在不存在任何其它润滑介质的情况下为磨损表面提供润滑，组分由压粉成小于理论密度的粉末金属形成，以便容纳孔隙，并且孔保持油。尽管组件沿其磨损表面机械加工，但孔仍然在磨损表面打开，以使夹带的油从环中渗出并润滑该表面。在环的制造过程中，机械加工在磨损表面产生Bielby层，即涂抹金属并封闭该表面的孔，但是通过放电加工去除Bielby层。该过程会将Bielby层与电弧，使得磨损表面处的孔再次暴露和打开。

68. 发明授权

US4571097A Tapered roller bearing with pressurized rib ring 失效
标题翻译：带加压肋环的圆锥滚子轴承
公开(公告)号：US4571097A
公开(公告)日：1986-02-18
申请号：US694441
申请日：1985-01-24
申请人： Peter W. Lee , Gary E. Kreider , Ronald L. Widner
发明人： Peter W. Lee , Gary E. Kreider , Ronald L. Widner
IPC分类号： F16C19/36 , F16C33/60 , F16C33/66
CPC分类号： F16C33/667 , F16C19/364 , F16C33/605 , F16C33/6674 , F16C33/6681
摘要： A tapered roller bearing has a rib ring against which the large ends of the tapered rollers for the bearing bear to prevent those rollers from being expelled from the annular space between the tapered raceways. The rib ring includes a porous, yet rigid, core and a jacket which covers the exposed surfaces of the core, except along an abutment face at which the large end faces of the rollers contact the rib ring. Here the pores of the core are exposed. The core at one of its other faces has a groove and the jacket has a port that opens into the groove. Pressurized oil is directed through the port and into the groove, from which it flows through the pores of the core and emerges at the abutment surface where it reduces friction between the abutment surface and the roller end faces.
摘要翻译：圆锥滚子轴承具有肋环，用于轴承的圆锥滚子的大端部能够抵靠该肋环，以防止这些辊从锥形滚道之间的环形空间排出。肋环包括多孔但刚性的芯和覆盖芯的暴露表面的护套，除了沿着辊的大端面接触肋环的邻接面之外。这里，核心的孔被暴露。其另一个面上的芯具有凹槽，并且护套具有通向凹槽的开口。加压油被引导通过端口并进入凹槽中，从而流过该芯的孔隙，并且出现在邻接表面处，从而减小邻接表面和辊端面之间的摩擦。

69. 发明授权

US08355287B2 Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device 失效
标题翻译：用于操作NAND类双电荷保持晶体管NOR闪存器件的方法和装置
公开(公告)号：US08355287B2
公开(公告)日：2013-01-15
申请号：US12806848
申请日：2010-08-23
申请人： Fu-Chang Hsu , Peter W. Lee
发明人： Fu-Chang Hsu , Peter W. Lee
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0458 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C16/3477 , G11C2211/5621
摘要： A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.
摘要翻译：用于NAND类型的双电荷保持晶体管NOR闪存单元的操作的方法和装置开始于擦除，验证将擦除的电荷保持晶体管的阈值电压电平擦除为已擦除的阈值电压电平。然后，通过将NAND类双电荷保持晶体管NOR闪存单元的两个电荷保持晶体管中的一个编程为第一编程阈值电压电平，并编程NAND类似的双电荷保持的两个电荷保持晶体管中的另一个来进行方法晶体管NOR闪存单元到第一编程阈值电压电平或第二编程阈值电压电平。擦除阈值电压电平和第一和第二编程阈值电压电平的组合确定NAND类似的双电荷保持晶体管NOR闪存单元的内部数据状态，然后对其进行解码以确定外部数据逻辑状态。

70. 发明授权

US07636252B2 Nonvolatile memory with a unified cell structure 有权
标题翻译：具有统一单元结构的非易失性存储器
公开(公告)号：US07636252B2
公开(公告)日：2009-12-22
申请号：US11483241
申请日：2006-07-07
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

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