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61. 发明授权

US08431933B2 Memory layout structure and memory structure 有权
标题翻译：内存布局结构和内存结构
公开(公告)号：US08431933B2
公开(公告)日：2013-04-30
申请号：US12874232
申请日：2010-09-02
申请人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
IPC分类号： H01L29/10
CPC分类号： H01L29/4983 , H01L27/0207 , H01L27/10855 , H01L27/10876 , H01L27/10882 , H01L29/4236
摘要： A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.
摘要翻译：公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸（边缘壁），以执行侧壁接触。自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

62. 发明授权

US07524205B1 Conducting wire anti-drop structure 失效
标题翻译：导线防滴结构
公开(公告)号：US07524205B1
公开(公告)日：2009-04-28
申请号：US12145114
申请日：2008-06-24
申请人： Tzung-Han Lee
发明人： Tzung-Han Lee
IPC分类号： H01R13/64
CPC分类号： H01R13/6392
摘要： The present invention is related to a conducting wire anti-drop structure for fixing two mutually connected conducting wires, which respectively have a connecting terminal for connecting with each other. The conducting wire anti-drop structure is characterized in that a positioning device is mounted on the connecting terminal of one of the conducting wires and has a positioning portion. The positioning portion is used to connect with a position-limiting device, which has an engaging portion extended from the connecting terminal for engaging with the other connecting terminal so as to limit the connection between the connecting terminals and provide stability.
摘要翻译：本发明涉及用于固定两个相互连接的导线的导线防滴结构，它们分别具有用于彼此连接的连接端子。导线防滴结构的特征在于，定位装置安装在一根导线的连接端子上，并具有定位部分。定位部用于与限位装置连接，该位置限制装置具有从连接端子延伸的接合部分，用于与另一连接端子接合，以限制连接端子之间的连接并提供稳定性。

63. 发明申请

US20080305605A1 METHOD FOR FORMING SURFACE STRAP 有权
标题翻译：形成表面带的方法
公开(公告)号：US20080305605A1
公开(公告)日：2008-12-11
申请号：US11940308
申请日：2007-11-14
申请人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
发明人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L21/20
CPC分类号： H01L27/10867
摘要： A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a selective ion implantation with an angle to make part of the poly-Si layer an undoped poly-Si layer; removing the undoped poly-Si layer to expose part of the conductive connection layer; etching the exposed conductive connection layer to form a recess; removing the poly-Si layer to make the exposed conductive connection layer a conductive connection strap; filling the recess with an insulation material to form a shallow trench isolation; exposing the conductive layer; and selectively removing the conductive layer to form a first conductive strap which forms the surface strap together with the conductive connection strap.
摘要翻译：一种形成表面带的方法包括：在其基板的表面上形成具有导电连接层的深沟槽电容器和与导电层接触的导电连接层; 形成覆盖所述焊盘层和所述导电连接层的多晶硅层; 以角度进行选择性离子注入，以使多晶硅层的一部分成为未掺杂的多晶硅层; 去除未掺杂的多晶硅层以暴露部分导电连接层; 蚀刻暴露的导电连接层以形成凹部; 去除所述多晶硅层以使所述暴露的导电连接层成为导电连接带; 用绝缘材料填充凹槽以形成浅沟槽隔离; 暴露导电层; 并且选择性地去除导电层以形成与导电连接带一起形成表面带的第一导电带。

64. 发明申请

US20080299734A1 Method of manufacturing a self-aligned fin field effect transistor (FinFET) device 审中-公开
标题翻译：制造自对准鳍状场效应晶体管（FinFET）器件的方法
公开(公告)号：US20080299734A1
公开(公告)日：2008-12-04
申请号：US11934044
申请日：2007-11-01
申请人： Tzung-Han Lee , Chin-Tien Yang
发明人： Tzung-Han Lee , Chin-Tien Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/7853 , H01L29/66818
摘要： A method of manufacturing a self-aligned fin FET (FinFET) device is disclosed, in which, an insulating layer of a shallow trench isolation is etched back to partially expose sidewalls of the semiconductor substrate surrounded by the shallow trench isolation, and the sidewalls of the semiconductor substrate are then isotropically etched, allowing the semiconductor substrate to form into a relatively thin fin structure for forming a three-dimensional gate structure having three faces.
摘要翻译：公开了一种制造自对准翅片FET（FinFET）器件的方法，其中将浅沟槽隔离的绝缘层回蚀刻以部分地暴露由浅沟槽隔离包围的半导体衬底的侧壁，并且侧壁然后各向同性蚀刻半导体衬底，使得半导体衬底形成相对薄的鳍结构，以形成具有三个面的三维栅极结构。

65. 发明授权

US07449741B2 SRAM cell structure and manufacturing method thereof 有权
公开(公告)号：US07449741B2
公开(公告)日：2008-11-11
申请号：US11416699
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

66. 发明申请

US20080251827A1 Checkerboard deep trench dynamic random access memory cell array layout 有权
标题翻译：棋盘深沟动态随机存取存储单元阵列布局
公开(公告)号：US20080251827A1
公开(公告)日：2008-10-16
申请号：US11776558
申请日：2007-07-12
申请人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
发明人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10885 , H01L27/10888 , Y10S257/905 , Y10S257/906
摘要： A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.
摘要翻译：公开了一种棋盘深沟动态随机存取存储单元阵列布局，其包括衬底，设置在衬底上的多个栅极导体线，嵌入在栅极导体下方的衬底中的多个棋盘布置且交错的深沟槽电容器结构线路，以及形成在栅极导体线下方的基板中的多个有源区域，交替布置有深沟槽电容器结构，并与相邻的深沟槽电容器结构电连接。深沟槽电容器结构之上的栅极导体线的部分的宽度比在有源区上方的栅极导体线的部分的宽度窄。

67. 发明授权

US07309890B2 SRAM cell structure and manufacturing method thereof 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US07309890B2
公开(公告)日：2007-12-18
申请号：US11416925
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L31/119
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

68. 发明授权

US06801435B1 Fixing structure for power supplies 有权
标题翻译：电源固定结构
公开(公告)号：US06801435B1
公开(公告)日：2004-10-05
申请号：US10437296
申请日：2003-05-14
申请人： Chun-Lung Su , Tzung-Han Lee , Hsien-Tang Weng
发明人： Chun-Lung Su , Tzung-Han Lee , Hsien-Tang Weng
IPC分类号： H05K502
CPC分类号： H05K7/1432 , Y10T292/0863 , Y10T292/0886 , Y10T292/0999
摘要： An improved fixing structure for power supplies defines an accommodating area on a power supply for installing a fixing structure, and the power supply has a fixing hole on a casing of the power supply defining a limit fixing condition for the fixing structure when the power supply is pushed into the casing, and the power supply has a limit hole for installing a limit fixing member to restrict the displacement of the fixing structure, and constitutes a fixing structure that can be installed directly inside a power supply without occupying additional space, and attains the effects of fixing two fixing structures and limiting the fixing member.
摘要翻译：电源的改进的固定结构限定了用于安装固定结构的电源上的容纳区域，并且电源具有在电源的壳体上的固定孔，限定当电源为并且电源具有用于安装极限固定构件以限制固定结构的位移的限制孔，并且构成可以直接安装在电源内而不占用额外空间的固定结构，并且达到固定两个固定结构并限制固定构件的效果。

69. 发明授权

US06754087B1 Power supply structure for high density servers 失效
标题翻译：高密度服务器的电源结构
公开(公告)号：US06754087B1
公开(公告)日：2004-06-22
申请号：US10352939
申请日：2003-01-29
申请人： Tzung-Han Lee , Edy Sung
发明人： Tzung-Han Lee , Edy Sung
IPC分类号： H05K718
CPC分类号： G06F1/184 , G06F1/188 , G06F1/20 , G06F1/26 , H05K7/1492
摘要： A power supply structure for high density servers bridging a system end and a power supply end includes a power receiving unit located on the system end, a power transmission unit located on the power supply end, and a conductive connection element connecting the power receiving unit and the power transmission unit through fasteners. The conductive connection element establishes electric connection with the power receiving unit and the power transmission unit through the fasteners so that power supply provided by the power supply end is transmitted from the power transmission unit to the conductive connection element which in turn transmits the power to the system end through the power receiving unit. The power supply structure of the invention may be assembled and installed quickly.
摘要翻译：用于桥接系统端和电源端的高密度服务器的电源结构包括位于系统端的电力接收单元，位于电源端的电力传输单元和连接电力接收单元和动力传动装置通过紧固件。导电连接元件通过紧固件与受电单元和动力传递单元建立电连接，使得由电力供应端提供的电力从动力传递单元传递到导电连接元件，导电连接元件又将功率传递到系统通过电力接收单元结束。本发明的电源结构可以快速组装和安装。

70. 发明授权

US06365454B1 Cylindrical capacitor structure and method of manufacture 失效
公开(公告)号：US06365454B1
公开(公告)日：2002-04-02
申请号：US09742465
申请日：2000-12-20
申请人： Tzung-Han Lee , Alex Hou , Kun-Chi Lin
发明人： Tzung-Han Lee , Alex Hou , Kun-Chi Lin
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10814 , H01L27/10855 , H01L28/84 , H01L28/91
摘要： A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate. Finally, conductive material is deposited into the node contact openings and the cylindrical openings to become the lower electrodes and the node contacts respectively.

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