专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07535045B2 Checkerboard deep trench dynamic random access memory cell array layout 有权
标题翻译：棋盘深沟动态随机存取存储单元阵列布局
公开(公告)号：US07535045B2
公开(公告)日：2009-05-19
申请号：US11776558
申请日：2007-07-12
申请人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
发明人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10885 , H01L27/10888 , Y10S257/905 , Y10S257/906
摘要： A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.
摘要翻译：公开了一种棋盘深沟动态随机存取存储单元阵列布局，其包括衬底，设置在衬底上的多个栅极导体线，嵌入在栅极导体下方的衬底中的多个棋盘布置且交错的深沟槽电容器结构线路，以及形成在栅极导体线下方的基板中的多个有源区域，交替布置有深沟槽电容器结构，并与相邻的深沟槽电容器结构电连接。深沟槽电容器结构之上的栅极导体线的部分的宽度比在有源区上方的栅极导体线的部分的宽度窄。

2. 发明申请

US20080299734A1 Method of manufacturing a self-aligned fin field effect transistor (FinFET) device 审中-公开
标题翻译：制造自对准鳍状场效应晶体管（FinFET）器件的方法
公开(公告)号：US20080299734A1
公开(公告)日：2008-12-04
申请号：US11934044
申请日：2007-11-01
申请人： Tzung-Han Lee , Chin-Tien Yang
发明人： Tzung-Han Lee , Chin-Tien Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/7853 , H01L29/66818
摘要： A method of manufacturing a self-aligned fin FET (FinFET) device is disclosed, in which, an insulating layer of a shallow trench isolation is etched back to partially expose sidewalls of the semiconductor substrate surrounded by the shallow trench isolation, and the sidewalls of the semiconductor substrate are then isotropically etched, allowing the semiconductor substrate to form into a relatively thin fin structure for forming a three-dimensional gate structure having three faces.
摘要翻译：公开了一种制造自对准翅片FET（FinFET）器件的方法，其中将浅沟槽隔离的绝缘层回蚀刻以部分地暴露由浅沟槽隔离包围的半导体衬底的侧壁，并且侧壁然后各向同性蚀刻半导体衬底，使得半导体衬底形成相对薄的鳍结构，以形成具有三个面的三维栅极结构。

3. 发明申请

US20080251827A1 Checkerboard deep trench dynamic random access memory cell array layout 有权
标题翻译：棋盘深沟动态随机存取存储单元阵列布局
公开(公告)号：US20080251827A1
公开(公告)日：2008-10-16
申请号：US11776558
申请日：2007-07-12
申请人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
发明人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10885 , H01L27/10888 , Y10S257/905 , Y10S257/906
摘要： A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.
摘要翻译：公开了一种棋盘深沟动态随机存取存储单元阵列布局，其包括衬底，设置在衬底上的多个栅极导体线，嵌入在栅极导体下方的衬底中的多个棋盘布置且交错的深沟槽电容器结构线路，以及形成在栅极导体线下方的基板中的多个有源区域，交替布置有深沟槽电容器结构，并与相邻的深沟槽电容器结构电连接。深沟槽电容器结构之上的栅极导体线的部分的宽度比在有源区上方的栅极导体线的部分的宽度窄。

4. 发明申请

US20130146954A1 Method Of Memory Array And Structure Form 审中-公开
标题翻译：存储器阵列和结构形式的方法
公开(公告)号：US20130146954A1
公开(公告)日：2013-06-13
申请号：US13429448
申请日：2012-03-26
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/0207 , H01L27/10876 , H01L27/10885
摘要： The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions.
摘要翻译：本发明提供了一种存储器阵列，其包括衬底，隔离区，多个有源区，多个掩埋位线，多个字线，多个漏极区和多个电容。隔离区域和有源区域设置在衬底中，并且有源区域被隔离区域包围和隔离。掩埋位线设置在基板中并沿第二方向延伸。字线设置在基板中沿第一方向延伸。漏极区域设置在未被字线覆盖的有源区域中。电容器设置在基板上并电连接到漏极区域。

5. 发明授权

US08309998B2 Memory structure having a floating body and method for fabricating the same 有权
标题翻译：具有浮体的存储结构及其制造方法
公开(公告)号：US08309998B2
公开(公告)日：2012-11-13
申请号：US13102039
申请日：2011-05-05
申请人： Tzung-Han Lee , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L29/7841 , H01L27/10802 , H01L29/66666 , H01L29/7827
摘要： A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided.
摘要翻译：提供一种具有浮体的存储器结构，其包括：衬底，其包括有源区域和围绕有源区域的隔离结构;有源区域中的衬底中的第一源极/漏极区域;位于衬底中的第一浮置体第一源极/漏极区域，第一浮体上的第二浮体，第二浮体上的第二源极/漏极区域，以及衬底中的沟槽型栅极结构以及第一浮体旁边。还提供了一种制造具有浮体的存储结构的方法。

6. 发明授权

US07960241B2 Manufacturing method for double-side capacitor of stack DRAM 有权
标题翻译：堆叠DRAM双面电容器制造方法
公开(公告)号：US07960241B2
公开(公告)日：2011-06-14
申请号：US12698322
申请日：2010-02-02
申请人： Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
发明人： Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L28/90
摘要： A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.
摘要翻译：堆叠DRAM的双面电容器的制造方法具有以下步骤：在隔离沟槽和电容器沟槽中形成牺牲结构; 在所述牺牲结构上形成第一覆盖层和第二覆盖层; 修改第二覆盖层的一部分; 去除未改性的第二覆盖层和第一覆盖层以暴露牺牲结构; 去除所述牺牲结构的暴露部分以暴露所述电极层; 去除暴露的电极层以暴露氧化物层; 并去除氧化物层和牺牲结构以形成双面电容器。

7. 发明授权

US07633109B2 DRAM structure and method of making the same 有权
标题翻译： DRAM结构和制作方法
公开(公告)号：US07633109B2
公开(公告)日：2009-12-15
申请号：US11965769
申请日：2007-12-28
申请人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
发明人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/66621 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/4236
摘要： A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.
摘要翻译： DRAM结构具有衬底，具有翅片结构的埋入晶体管，沟槽电容器和衬底表面上的表面带。表面带用于将漏极区域电连接到沟槽电容器。

8. 发明授权

US07615443B2 Method of forming finFET device 有权
标题翻译：形成finFET器件的方法
公开(公告)号：US07615443B2
公开(公告)日：2009-11-10
申请号：US12030210
申请日：2008-02-13
申请人： Chih-Hao Cheng , Tzung-Han Lee
发明人： Chih-Hao Cheng , Tzung-Han Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879
摘要： The invention discloses a method of forming a finFET device. A hard mask layer is formed on an active area of a semiconductor substrate. A portion of the hard mask layer is etched to form a recess. A conformal gate defining layer is deposited on the recess and a tilt angle ion implantation process is performed. A part of the gate defining layer is removed to define a fin pattern. The fin pattern is subsequently transferred to the hard mask layer. The patterned hard mask layer having the fin pattern is utilized as an etching mask, and the semiconductor substrate is etched to form a fin structure.
摘要翻译：本发明公开了一种形成finFET器件的方法。在半导体衬底的有源区上形成硬掩模层。硬掩模层的一部分被蚀刻以形成凹部。在凹槽上沉积保形栅极限定层，并执行倾斜角度离子注入工艺。去除栅极限定层的一部分以限定鳍状图案。翅片图案随后转移到硬掩模层。将具有翅片图案的图案化的硬掩模层用作蚀刻掩模，并且蚀刻半导体衬底以形成翅片结构。

9. 发明申请

US20070298567A1 SRAM CELL STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US20070298567A1
公开(公告)日：2007-12-27
申请号：US11852185
申请日：2007-09-07
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rem-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rem-Hurng Larn
IPC分类号： H01L21/8244
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

10. 发明授权

US07157763B2 SRAM cell structure and manufacturing method thereof 有权
公开(公告)号：US07157763B2
公开(公告)日：2007-01-02
申请号：US10983140
申请日：2004-11-04
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式