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61. 发明申请

US20120269011A1 VOLTAGE SWITCHING IN A MEMORY DEVICE 有权
标题翻译：存储器件中的电压开关
公开(公告)号：US20120269011A1
公开(公告)日：2012-10-25
申请号：US13542250
申请日：2012-07-05
申请人： Giulio G. Marotta , Carlo Musilli , Stefano Perugini , Alessandro Torsi , Tommaso Vali
发明人： Giulio G. Marotta , Carlo Musilli , Stefano Perugini , Alessandro Torsi , Tommaso Vali
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C7/12 , H03K3/35613 , H03K19/018528
摘要： Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.
摘要翻译：公开了电压开关，存储器件，存储器系统和用于切换的方法。一个这样的电压开关使用串联耦合的一对开关电路，每个开关电路由电平移位电路驱动。每个开关电路使用具有并联控制晶体管的一组串联耦合晶体管，其中每组中的晶体管数量可由每个晶体管的预期开关输入电压和最大允许电压降确定。使能信号的特定状态的电压由电平移位电路移动到开关输入电压。使能信号的特定状态使电压开关导通，使得开关输出电压基本上等于开关输入电压。

62. 发明申请

US20110273219A1 VOLTAGE SWITCHING IN A MEMORY DEVICE 有权
标题翻译：存储器件中的电压开关
公开(公告)号：US20110273219A1
公开(公告)日：2011-11-10
申请号：US12775131
申请日：2010-05-06
申请人： Giulio G. Marotta , Carlo Musilli , Stefano Perugini , Alessandro Torsi , Tommaso Vali
发明人： Giulio G. Marotta , Carlo Musilli , Stefano Perugini , Alessandro Torsi , Tommaso Vali
IPC分类号： H03K17/687
CPC分类号： G11C7/12 , H03K3/35613 , H03K19/018528
摘要： Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.
摘要翻译：公开了电压开关，存储器件，存储器系统和用于切换的方法。一个这样的电压开关使用串联耦合的一对开关电路，每个开关电路由电平移位电路驱动。每个开关电路使用具有并联控制晶体管的一组串联耦合晶体管，其中每组中的晶体管数量可由每个晶体管的预期开关输入电压和最大允许电压降确定。使能信号的特定状态的电压由电平移位电路移动到开关输入电压。使能信号的特定状态使电压开关导通，使得开关输出电压基本上等于开关输入电压。

63. 发明授权

US07417894B2 Single latch data circuit in a multiple level cell non-volatile memory device 有权
标题翻译：单级锁存数据电路在多级单元非易失性存储器件中
公开(公告)号：US07417894B2
公开(公告)日：2008-08-26
申请号：US11506428
申请日：2006-08-18
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

64. 发明授权

US07324383B2 Selective slow programming convergence in a flash memory device 有权
标题翻译：闪存设备中选择性慢的编程收敛
公开(公告)号：US07324383B2
公开(公告)日：2008-01-29
申请号：US11414982
申请日：2006-05-01
申请人： Michele Incarnati , Giovanni Santin , Tommaso Vali
发明人： Michele Incarnati , Giovanni Santin , Tommaso Vali
IPC分类号： G11C16/06
CPC分类号： G11C16/3404
摘要： A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.
摘要翻译：多个存储器单元被编程，其中增加的编程脉冲被施加到存储器单元耦合到的字线。在每个脉冲之后，验证操作确定每个单元的阈值电压。当阈值电压达到预验证阈值时，只有连接到该特定单元的位线被中间电压偏置，该中间电压降低了单元的Vcc变化。其他细胞继续按其正常速度进行编程。由于每个单元的V OUT达到预验证电平，所以它被中间电压偏置。当它们的阈值电压达到验证电压阈值时，所有位线都被抑制电压偏置。

65. 发明授权

US07200041B2 Sensing scheme for low-voltage flash memory 有权
标题翻译：低压闪存检测方案
公开(公告)号：US07200041B2
公开(公告)日：2007-04-03
申请号：US10932489
申请日：2004-09-02
申请人： Giulio G. Marotta , Tommaso Vali
发明人： Giulio G. Marotta , Tommaso Vali
IPC分类号： G11C11/34
CPC分类号： G11C7/04 , G11C7/14 , G11C16/24 , G11C16/26
摘要： Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device has an input node selectively coupled to the memory cell. The sensing device includes a precharging path for applying a precharge potential to the input node of the sensing device for precharging bit lines prior to sensing the programmed state of the memory cell, and a reference current path for applying a reference current to the input node of the sensing device. The sensing device still further includes a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the memory cell.
摘要翻译：用于感测浮栅存储器单元的编程状态的单端感测装置适用于低电压存储器件。感测装置具有选择性地耦合到存储单元的输入节点。感测装置包括用于将预充电电位施加到感测装置的输入节点的预充电路径，用于在感测存储器单元的编程状态之前对位线进行预充电，以及用于将参考电流施加到输入节点的参考电流路径感测装置。感测装置还包括感测反相器，其具有耦合到感测装置的输入节点的输入和用于提供指示存储器单元的编程状态的输出信号的输出。在感测存储器单元的编程状态期间，将参考电流施加到感测装置的输入节点。

66. 发明授权

US07164607B2 Dual bus memory burst architecture 有权
标题翻译：双总线内存突发架构
公开(公告)号：US07164607B2
公开(公告)日：2007-01-16
申请号：US11142114
申请日：2005-06-01
申请人： Girolamo Gallo , Giuliano Gennaro Imondi , Giovanni Naso , Tommaso Vali
发明人： Girolamo Gallo , Giuliano Gennaro Imondi , Giovanni Naso , Tommaso Vali
IPC分类号： G11C7/10
CPC分类号： G11C7/106 , G11C7/1021 , G11C7/103 , G11C7/1051 , G11C7/1066
摘要： Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.
摘要翻译：包括突发体系结构的存储器件的方法和装置采用复用到输出总线上的双总线架构。所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。

67. 发明授权

US07145799B2 Chip protection register unlocking 有权
标题翻译：芯片保护寄存器解锁
公开(公告)号：US07145799B2
公开(公告)日：2006-12-05
申请号：US11170880
申请日：2005-06-30
申请人： Giovanni Naso , Pietro Piersimoni , Tommaso Vali
发明人： Giovanni Naso , Pietro Piersimoni , Tommaso Vali
IPC分类号： G11C16/22
CPC分类号： G11C7/24 , G11C16/22 , G11C2029/4402
摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.
摘要翻译：用保护寄存器锁定位擦除使能电路描述改进的闪速存储器件。当单独的闪存芯片晶片被封装时，耦合到改进的闪速存储器的锁定位擦除使能电路的接合焊盘不被接合。这允许存储器制造商通过测试卡探针访问焊盘并擦除锁定位，同时芯片仍然是晶片形式，但是当芯片晶片被封装时，使得锁定位有效地不可靠。这使得内存芯片制造商能够通过彻底测试锁定位和保护寄存器功能来增强闪存设备的可靠性和容错能力。此外，锁定位擦除使能电路通过允许存储器芯片制造商在组织改变或保护寄存器的无意或错误编程的情况下重新编程保护寄存器和锁定位来提高制造灵活性。

68. 发明授权

US07143255B2 Chip protection register lock circuit in a flash memory device 有权
标题翻译：芯片保护寄存器锁定电路在闪存设备中
公开(公告)号：US07143255B2
公开(公告)日：2006-11-28
申请号：US10854397
申请日：2004-05-26
申请人： Luca De Santis , Tommaso Vali
发明人： Luca De Santis , Tommaso Vali
IPC分类号： G06F12/14
CPC分类号： G11C16/22
摘要： A chip protection register lock circuit uses a plurality of lock bits in a lock bit register. If the register contains N bits, N/2 bits of the register are coupled to an erase circuit and the remaining N/2 bits are coupled to a programming circuit. After the chip protection register is programmed, the group of N/2 bits coupled to the erase circuit are erased and the remaining N/2 bits are programmed such that an alternating pattern of logical ones and zeros are in the lock bit register. A read and compare circuit generates a lock indication if the alternating pattern is present.
摘要翻译：芯片保护寄存器锁定电路在锁定位寄存器中使用多个锁定位。如果寄存器包含N位，则寄存器的N / 2位耦合到擦除电路，剩余的N / 2位耦合到编程电路。在编程芯片保护寄存器之后，擦除与擦除电路相关的N / 2位的组，并对其余的N / 2位进行编程，使得逻辑1和0的交替模式位于锁定位寄存器中。如果存在交替模式，则读取和比较电路产生锁定指示。

69. 发明申请

US20050237810A1 Sense amplifier for a non-volatile memory device 有权
标题翻译：用于非易失性存储器件的感应放大器
公开(公告)号：US20050237810A1
公开(公告)日：2005-10-27
申请号：US10912520
申请日：2004-08-05
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C7/06 , G11C7/12 , G11C7/18 , G11C11/34 , G11C16/24 , G11C16/26
CPC分类号： G11C7/12 , G11C7/067 , G11C7/18 , G11C16/24 , G11C16/26
摘要： The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.
摘要翻译：存储器件具有多个存储单元，每个存储器单元都耦合到位线。反馈晶体管耦合到位线，并对位线的预充电状态提供电压反馈。偏置晶体管耦合到反馈晶体管。偏置晶体管响应于偏置晶体管上的参考电压向反馈晶体管提供偏置电压。共源共栅连接的晶体管耦合到反馈晶体管和偏置晶体管。该晶体管向偏置晶体管提供稳定的偏置电压。输出锁存电路耦合到位线以提供存储器单元数据的锁存输出。

70. 发明申请

US20050207233A1 Dual bus memory burst architecture 有权
标题翻译：双总线内存突发架构
公开(公告)号：US20050207233A1
公开(公告)日：2005-09-22
申请号：US11142114
申请日：2005-06-01
申请人： Girolamo Gallo , Giuliano Imondi , Giovanni Naso , Tommaso Vali
发明人： Girolamo Gallo , Giuliano Imondi , Giovanni Naso , Tommaso Vali
IPC分类号： G11C7/10 , G11C5/00
CPC分类号： G11C7/106 , G11C7/1021 , G11C7/103 , G11C7/1051 , G11C7/1066
摘要： Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.
摘要翻译：包括突发体系结构的存储器件的方法和装置采用复用到输出总线上的双总线架构。所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。

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