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1. 发明授权

US08233329B2 Architecture and method for memory programming 有权
标题翻译：内存编程的架构和方法
公开(公告)号：US08233329B2
公开(公告)日：2012-07-31
申请号：US12365589
申请日：2009-02-04
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

2. 发明授权

US07394699B2 Sense amplifier for a non-volatile memory device 有权
标题翻译：用于非易失性存储器件的感应放大器
公开(公告)号：US07394699B2
公开(公告)日：2008-07-01
申请号：US11651687
申请日：2007-01-10
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.
摘要翻译：存储器件具有多个存储单元，每个存储器单元都耦合到位线。反馈晶体管耦合到位线，并对位线的预充电状态提供电压反馈。偏置晶体管耦合到反馈晶体管。偏置晶体管响应于偏置晶体管上的参考电压向反馈晶体管提供偏置电压。共源共栅连接的晶体管耦合到反馈晶体管和偏置晶体管。该晶体管向偏置晶体管提供稳定的偏置电压。输出锁存电路耦合到位线以提供存储器单元数据的锁存输出。

3. 发明申请

US20070115742A1 Sense amplifier for a non-volatile memory device 有权
公开(公告)号：US20070115742A1
公开(公告)日：2007-05-24
申请号：US11651687
申请日：2007-01-10
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C7/00
CPC分类号： G11C16/26
摘要： The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.

4. 发明授权

US07173856B2 Sense amplifier for a non-volatile memory device 有权
标题翻译：用于非易失性存储器件的感应放大器
公开(公告)号：US07173856B2
公开(公告)日：2007-02-06
申请号：US10912520
申请日：2004-08-05
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/06 , G11C7/02
CPC分类号： G11C7/12 , G11C7/067 , G11C7/18 , G11C16/24 , G11C16/26
摘要： The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.
摘要翻译：存储器件具有多个存储单元，每个存储器单元都耦合到位线。反馈晶体管耦合到位线，并对位线的预充电状态提供电压反馈。偏置晶体管耦合到反馈晶体管。偏置晶体管响应于偏置晶体管上的参考电压向反馈晶体管提供偏置电压。共源共栅连接的晶体管耦合到反馈晶体管和偏置晶体管。该晶体管向偏置晶体管提供稳定的偏置电压。输出锁存电路耦合到位线以提供存储器单元数据的锁存输出。

5. 发明申请

US20060285392A1 Selective slow programming convergence in a flash memory device 有权
标题翻译：闪存设备中选择性慢编程收敛
公开(公告)号：US20060285392A1
公开(公告)日：2006-12-21
申请号：US11414982
申请日：2006-05-01
申请人： Michele Incarnati , Giovanni Santin , Tommaso Vali
发明人： Michele Incarnati , Giovanni Santin , Tommaso Vali
IPC分类号： G11C11/34
CPC分类号： G11C16/3404
摘要： A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.
摘要翻译：多个存储器单元被编程，其中增加的编程脉冲被施加到存储器单元耦合到的字线。在每个脉冲之后，验证操作确定每个单元的阈值电压。当阈值电压达到预验证阈值时，只有连接到该特定单元的位线被中间电压偏置，该中间电压降低了单元的Vcc变化。其他细胞继续按其正常速度进行编程。由于每个单元的V OUT达到预验证电平，所以它被中间电压偏置。当它们的阈值电压达到验证电压阈值时，所有位线都被抑制电压偏置。

6. 发明申请

US20060098497A1 Method and apparatus for filtering output data 有权
标题翻译：用于过滤输出数据的方法和装置
公开(公告)号：US20060098497A1
公开(公告)日：2006-05-11
申请号：US11127526
申请日：2005-05-12
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/22 , G11C2207/2281
摘要： Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option.
摘要翻译：用自适应滤波电路滤波杂散输出转换的装置和方法，该自适应滤波电路以降低的速度损失跟踪存储器架构和形状因子。滤波可由保险丝选项选择。

7. 发明申请

US20120287726A1 ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING 有权
标题翻译：用于存储器编程的架构和方法
公开(公告)号：US20120287726A1
公开(公告)日：2012-11-15
申请号：US13561248
申请日：2012-07-30
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

8. 发明申请

US20100091582A1 ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING 有权
标题翻译：用于存储器编程的架构和方法
公开(公告)号：US20100091582A1
公开(公告)日：2010-04-15
申请号：US12365589
申请日：2009-02-04
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

9. 发明授权

US07417894B2 Single latch data circuit in a multiple level cell non-volatile memory device 有权
标题翻译：单级锁存数据电路在多级单元非易失性存储器件中
公开(公告)号：US07417894B2
公开(公告)日：2008-08-26
申请号：US11506428
申请日：2006-08-18
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

10. 发明授权

US07324383B2 Selective slow programming convergence in a flash memory device 有权
标题翻译：闪存设备中选择性慢的编程收敛
公开(公告)号：US07324383B2
公开(公告)日：2008-01-29
申请号：US11414982
申请日：2006-05-01
申请人： Michele Incarnati , Giovanni Santin , Tommaso Vali
发明人： Michele Incarnati , Giovanni Santin , Tommaso Vali
IPC分类号： G11C16/06
CPC分类号： G11C16/3404
摘要： A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.
摘要翻译：多个存储器单元被编程，其中增加的编程脉冲被施加到存储器单元耦合到的字线。在每个脉冲之后，验证操作确定每个单元的阈值电压。当阈值电压达到预验证阈值时，只有连接到该特定单元的位线被中间电压偏置，该中间电压降低了单元的Vcc变化。其他细胞继续按其正常速度进行编程。由于每个单元的V OUT达到预验证电平，所以它被中间电压偏置。当它们的阈值电压达到验证电压阈值时，所有位线都被抑制电压偏置。

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