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61. 发明授权

US07897453B2 Dual insulating layer diode with asymmetric interface state and method of fabrication 有权
标题翻译：具有非对称界面状态和制造方法的双重绝缘层二极管
公开(公告)号：US07897453B2
公开(公告)日：2011-03-01
申请号：US12336410
申请日：2008-12-16
申请人： Xiying Chen , Deepak Chandra Sekar , Mark Clark , Dat Nguyen , Tanmay Kumar
发明人： Xiying Chen , Deepak Chandra Sekar , Mark Clark , Dat Nguyen , Tanmay Kumar
IPC分类号： H01L21/8234
CPC分类号： H01L27/2481 , H01L27/2418 , H01L45/00
摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors.
摘要翻译：提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。二极管是具有第一金属层，第一绝缘层，第二绝缘层和第二金属层的金属绝缘体二极管。在至少两个层的交叉处提供至少一个非对称界面状态，以增加二极管的导通电流与其反向偏置漏电流的比率。在各种示例中，非对称界面状态由改变二极管的一个或多个部分处的势垒高度和/或电场的正或负片电荷形成。诸如无源元件存储单元的两端器件可以将二极管用作与状态改变元件串联的转向元件。可以在上下导体的交点处使用支柱结构形成装置。

62. 发明授权

US07830698B2 Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same 有权
标题翻译：含有碳储存材料的多层非易失性存储器件及其制造和使用方法
公开(公告)号：US07830698B2
公开(公告)日：2010-11-09
申请号：US12153872
申请日：2008-05-27
申请人： Xiying Chen , Bing K. Yen , Dat Nguyen , Huiwen Xu , George Samachisa , Tanmay Kumar , Er-Xuan Ping
发明人： Xiying Chen , Bing K. Yen , Dat Nguyen , Huiwen Xu , George Samachisa , Tanmay Kumar , Er-Xuan Ping
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/00 , G11C13/0069 , G11C13/025 , G11C2013/009 , G11C2213/35 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/149 , H01L45/1616 , H01L45/1675
摘要： A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels.
摘要翻译：非易失性存储单元包括与存储元件串联定位的转向元件。存储元件包括碳材料，并且存储单元包括具有多个存储器级别的可重写单元。

63. 发明申请

US20100148324A1 Dual Insulating Layer Diode With Asymmetric Interface State And Method Of Fabrication 有权
标题翻译：双绝缘层二极管与不对称接口状态及制作方法
公开(公告)号：US20100148324A1
公开(公告)日：2010-06-17
申请号：US12336410
申请日：2008-12-16
申请人： Xiying Chen , Deepak Chandra Sekar , Mark Clark , Dat Nguyen , Tanmay Kumar
发明人： Xiying Chen , Deepak Chandra Sekar , Mark Clark , Dat Nguyen , Tanmay Kumar
IPC分类号： H01L29/868
CPC分类号： H01L27/2481 , H01L27/2418 , H01L45/00
摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors.
摘要翻译：提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。二极管是具有第一金属层，第一绝缘层，第二绝缘层和第二金属层的金属绝缘体二极管。在至少两个层的交叉处提供至少一个非对称界面状态，以增加二极管的导通电流与其反向偏置漏电流的比率。在各种示例中，非对称界面状态由改变二极管的一个或多个部分处的势垒高度和/或电场的正或负片电荷形成。诸如无源元件存储单元的两端器件可以将二极管用作与状态改变元件串联的转向元件。可以在上下导体的交点处使用支柱结构形成装置。

64. 发明授权

US07706169B2 Large capacity one-time programmable memory cell using metal oxides 失效
标题翻译：大容量一次性可编程存储单元，使用金属氧化物
公开(公告)号：US07706169B2
公开(公告)日：2010-04-27
申请号：US12005277
申请日：2007-12-27
申请人： Tanmay Kumar
发明人： Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0078 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/72
摘要： A method of programming a nonvolatile memory device includes (i) providing a nonvolatile memory cell comprising a diode in series with at least one metal oxide, (ii) applying a first forward bias to change a resistivity state of the metal oxide from a first state to a second state; (iii) applying a second forward bias to change a resistivity state of the metal oxide from a second state to a third state; and (iv) applying a third forward bias to change a resistivity state of the metal oxide from a third state to a fourth state. The fourth resistivity state is higher than the third resistivity state, the third resistivity state is lower than the second resistivity state, and the second resistivity state is lower than the first resistivity state.
摘要翻译：非易失性存储器件的编程方法包括：（i）提供包括与至少一种金属氧化物串联的二极管的非易失性存储单元，（ii）施加第一正向偏压以从第一状态改变金属氧化物的电阻率状态到第二个状态（iii）施加第二正向偏压以将金属氧化物的电阻率状态从第二状态改变到第三状态; 和（iv）施加第三正向偏压以将金属氧化物的电阻率状态从第三状态改变到第四状态。第四电阻率状态高于第三电阻率状态，第三电阻率状态低于第二电阻率状态，第二电阻率状态低于第一电阻率状态。

65. 发明申请

US20100078759A1 MIIM DIODES HAVING STACKED STRUCTURE 有权
标题翻译：具有堆叠结构的MIIM二极管
公开(公告)号：US20100078759A1
公开(公告)日：2010-04-01
申请号：US12240785
申请日：2008-09-29
申请人： Deepak C. Sekar , Tanmay Kumar , Peter Rabkin , Er-Xuan Ping , Xiying Chen
发明人： Deepak C. Sekar , Tanmay Kumar , Peter Rabkin , Er-Xuan Ping , Xiying Chen
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L45/00 , H01L27/2418 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/144 , H01L45/149
摘要： A metal-insulator diode is disclosed. In one aspect, the metal-insulator diode comprises first and second electrode and first and second insulators arraigned as follows. An insulating region has a trench formed therein. The trench has a bottom and side walls. The first electrode, which comprises a first metal, is on the side walls and over the bottom of the trench. A first insulator has a first interface with the first electrode. At least a portion of the first insulator is within the trench. A second insulator has a second interface with the first insulator. At least a portion of the second insulator is within the trench. The second electrode, which comprises a second metal, is in contact with the second insulator. The second electrode at least partially fills the trench.
摘要翻译：公开了一种金属绝缘体二极管。在一个方面，金属绝缘体二极管包括第一和第二电极以及第一和第二绝缘体，如下所述。绝缘区域中形成有沟槽。沟槽有一个底部和侧壁。第一电极包括第一金属，位于沟槽的侧壁和底部的上方。第一绝缘体具有与第一电极的第一界面。第一绝缘体的至少一部分在沟槽内。第二绝缘体具有与第一绝缘体的第二接口。第二绝缘体的至少一部分在沟槽内。包括第二金属的第二电极与第二绝缘体接触。第二电极至少部分地填充沟槽。

66. 发明申请

US20090258462A1 METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS 有权
标题翻译：通过连接多晶硅层形成掺杂多晶硅的方法
公开(公告)号：US20090258462A1
公开(公告)日：2009-10-15
申请号：US12489214
申请日：2009-06-22
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/82
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

67. 发明申请

US20090257266A1 Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same 有权
标题翻译：含有碳储存材料的多层非易失性存储器件及其制造和使用方法
公开(公告)号：US20090257266A1
公开(公告)日：2009-10-15
申请号：US12153873
申请日：2008-05-27
申请人： Xiying Chen , Tanmay Kumar
发明人： Xiying Chen , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , B82Y10/00 , G11C11/56 , G11C13/0069 , G11C13/025 , G11C17/16 , G11C17/165 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/19 , G11C2213/35 , G11C2213/72
摘要： A method of programming a nonvolatile memory cell includes applying at least one initialization pulse having a duration of at least 1 ms, followed by applying plural programming pulses having a duration of less than 1 ms. The cell includes a steering element located in series with a storage element, and the storage element includes a carbon material.
摘要翻译：非易失性存储单元的编程方法包括施加至少一个具有至少1ms的持续时间的初始化脉冲，然后施加持续时间小于1ms的多个编程脉冲。电池包括与存储元件串联设置的转向元件，并且存储元件包括碳材料。

68. 发明授权

US07492630B2 Systems for reverse bias trim operations in non-volatile memory 有权
标题翻译：用于非易失性存储器中的反向偏置调整操作的系统
公开(公告)号：US07492630B2
公开(公告)日：2009-02-17
申请号：US11461431
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tanmay Kumar
发明人： Roy E. Scheuerlein , Tanmay Kumar
IPC分类号： G11C13/04
CPC分类号： G11C8/08 , G11C5/02 , G11C11/56 , G11C13/0023 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C17/16 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.
摘要翻译：公开了一种用于非易失性存储器系统的复位状态的反偏压调整操作。包括电阻变化元件的非易失性存储单元经历反向偏置复位操作，以在第二电阻电平下将其电阻从第一电阻上的设定状态改变为复位状态。复位的一组单元格中的某些存储单元可能被重新设置为超出复位状态的目标电平的电阻水平。第二反向偏压被施加到存储器单元组，以将每个单元的电阻移动到复位状态的目标电平。与用于复位操作相比较小的反向偏压可以将电池的电阻转移回设定电平并脱离它们的深度复位状态。操作是自限制的，因为细胞在达到目标水平时停止其阻力位移。未重新设置的单元格不受影响。

69. 发明申请

US20080025077A1 SYSTEMS FOR CONTROLLED PULSE OPERATIONS IN NON-VOLATILE MEMORY 有权
标题翻译：在非易失性存储器中控制脉冲运行的系统
公开(公告)号：US20080025077A1
公开(公告)日：2008-01-31
申请号：US11461399
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tanmay Kumar
发明人： Roy E. Scheuerlein , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C5/145 , G11C5/02 , G11C8/08 , G11C13/0023 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C17/16 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.
摘要翻译：提供了一种无源元件存储器件，其包括由与转向元件串联的状态改变元件构成的存储单元。受控脉冲操作用于执行与存储器单元阵列中的置位和复位操作相关的电阻变化。在一个实施例中，通过对所选择的第一阵列线施加正电压脉冲同时向所选择的第二阵列线施加负电压脉冲，将阵列中的选定存储单元切换到目标电阻状态。可以增加电压脉冲的幅度，同时施加以有效和安全地切换具有不同操作特性的电池的电阻。在实施例中，电池经受反向偏置以降低泄漏电流并增加带宽。在一些实施例中，电压脉冲的幅度和持续时间与在选择的存储器单元上施加的电流一起被控制。这些受控的基于脉冲的操作可以用于在各种实施例中将存储器单元设置为较低的电阻状态或将存储器单元重置为更高的电阻状态。

70. 发明申请

US20080013364A1 Method of making non-volatile memory cell with embedded antifuse 有权
标题翻译：制造具有嵌入式反熔丝的非易失性存储单元的方法
公开(公告)号：US20080013364A1
公开(公告)日：2008-01-17
申请号：US11819595
申请日：2007-06-28
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： G11C11/00 , H01L21/336
CPC分类号： G11C5/02 , G11C11/39 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0676
摘要： A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.
摘要翻译：制造非易失性存储器件的方法包括形成第一电极，形成至少一个非易失性存储单元，该非易失性存储单元包括第一二极管部分，第二二极管部分和将第一二极管部分与第二二极管部分分离的反熔丝，以及形成第二电极在所述至少一个非易失性存储单元上。

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