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1. 发明申请

US20090258462A1 METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS 有权
标题翻译：通过连接多晶硅层形成掺杂多晶硅的方法
公开(公告)号：US20090258462A1
公开(公告)日：2009-10-15
申请号：US12489214
申请日：2009-06-22
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/82
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

2. 发明申请

US20110021019A1 METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS 有权
标题翻译：通过连接多晶硅层形成掺杂多晶硅的方法
公开(公告)号：US20110021019A1
公开(公告)日：2011-01-27
申请号：US12897696
申请日：2010-10-04
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/768
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

3. 发明授权

US07915164B2 Method for forming doped polysilicon via connecting polysilicon layers 有权
公开(公告)号：US07915164B2
公开(公告)日：2011-03-29
申请号：US12897696
申请日：2010-10-04
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/8246 , H01L21/768
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

4. 发明授权

US07915163B2 Method for forming doped polysilicon via connecting polysilicon layers 有权
标题翻译：通过连接多晶硅层形成掺杂多晶硅的方法
公开(公告)号：US07915163B2
公开(公告)日：2011-03-29
申请号：US12489214
申请日：2009-06-22
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/8246 , H01L21/768
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

5. 发明授权

US07566974B2 Doped polysilicon via connecting polysilicon layers 有权
标题翻译：掺杂多晶硅通过连接多晶硅层
公开(公告)号：US07566974B2
公开(公告)日：2009-07-28
申请号：US10955710
申请日：2004-09-29
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Tanmay Kumar , Sucheta Nallamothu , Andrew J. Walker
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Tanmay Kumar , Sucheta Nallamothu , Andrew J. Walker
IPC分类号： H01L23/48 , H01L23/52 , H01L29/43
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

6. 发明申请

US20060071074A1 Doped polysilicon via connecting polysilicon layers 有权
公开(公告)号：US20060071074A1
公开(公告)日：2006-04-06
申请号：US10955710
申请日：2004-09-29
申请人： Michael Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew Walker , Tanmay Kumar
发明人： Michael Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew Walker , Tanmay Kumar
IPC分类号： G06K7/10
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

7. 发明授权

US08298931B2 Dual damascene with amorphous carbon for 3D deep via/trench application 有权
标题翻译：双重镶嵌无定形碳，用于3D深通孔/沟槽应用
公开(公告)号：US08298931B2
公开(公告)日：2012-10-30
申请号：US11864759
申请日：2007-09-28
申请人： Usha Raghuram , Michael W. Konevecki
发明人： Usha Raghuram , Michael W. Konevecki
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L27/101 , H01L27/1021
摘要： A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 μm. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask.
摘要翻译：一种用于制造使用无定形碳硬掩模蚀刻通孔和沟槽的3-D单片存储器件的方法。该通孔作为多级垂直互连在设备的多个级别中延伸。沟槽横向延伸，例如为存储器单元提供字线或位线，或提供其它布线路径。可以使用双镶嵌工艺，其中通孔首先形成并且沟槽形成第二，或者沟槽首先形成，并且通孔形成第二。该技术特别适用于深通孔应用，例如大于1μm的通孔深度。可以使用任选具有底部抗反射涂层的电介质抗反射涂层来蚀刻无定形碳层以提供无定形碳硬掩模。

8. 发明申请

US20070284656A1 Conductive hard mask to protect patterned features during trench etch 失效
标题翻译：导电硬掩模，用于在沟槽蚀刻期间保护图案特征
公开(公告)号：US20070284656A1
公开(公告)日：2007-12-13
申请号：US11444936
申请日：2006-05-31
申请人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
发明人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L23/5252 , H01L27/1021 , H01L29/6609 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.
摘要翻译：提供了一种使用导电硬掩模形成图案化特征的方法，其中导电硬掩模在随后的沟槽蚀刻期间保护这些特征以形成提供从上方到那些特征的电连接的大马士革导体。硬掩模的厚度提供了一个余量，以避免在沟槽蚀刻期间的过蚀刻，这可能对器件性能有害。该方法有利地用于形成单片三维存储器阵列。

9. 发明授权

US07307013B2 Nonselective unpatterned etchback to expose buried patterned features 失效
标题翻译：曝光掩埋图案特征的无选择性无图案蚀刻
公开(公告)号：US07307013B2
公开(公告)日：2007-12-11
申请号：US10883417
申请日：2004-06-30
申请人： Usha Raghuram , Michael W. Konevecki , Samuel V. Dunton
发明人： Usha Raghuram , Michael W. Konevecki , Samuel V. Dunton
IPC分类号： H01L21/461 , C03C25/68 , C23F1/00
CPC分类号： H01L21/7684 , H01L21/31055 , H01L21/31116 , H01L21/32136 , H01L21/32137 , H01L21/76819 , H01L27/101 , H01L27/1021
摘要： A method for etching to form a planarized surface is disclosed. Spaced-apart features are formed of a first material, the first material either conductive or insulating. A second material is deposited over and between the first material. The second material is either insulating or conductive, opposite the conductivity of the first material. The second material is preferably self-planarizing during deposition. An unpatterned etch is performed to etch the second material and expose the top of the buried features of the first material. The etch is preferably a two-stage etch: The first stage is selective to the second material. When the second material is exposed, the etch chemistry is changed such that the etch is nonselective, etching the first material and the second material at substantially the same rate until the buried features are exposed across the wafer, producing a substantially planar surface.
摘要翻译：公开了一种用于蚀刻以形成平坦化表面的方法。隔开的特征由第一材料形成，第一材料是导电的或绝缘的。第二材料沉积在第一材料之上和之间。第二种材料是绝缘的或导电的，与第一种材料的电导率相反。第二种材料优选在沉积期间是自平面化的。执行未图案化的蚀刻以蚀刻第二材料并暴露第一材料的掩埋特征的顶部。蚀刻优选是两阶段蚀刻：第一阶段对第二材料是选择性的。当暴露第二材料时，蚀刻化学物质被改变，使得蚀刻是非选择性的，以基本上相同的速率蚀刻第一材料和第二材料，直到掩埋特征暴露在晶片之外，产生基本平坦的表面。

10. 发明申请

US20090273022A1 CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH 审中-公开
标题翻译：导电硬掩模，以保护在TRENCH ETCH期间的图案特征
公开(公告)号：US20090273022A1
公开(公告)日：2009-11-05
申请号：US12502796
申请日：2009-07-14
申请人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
发明人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
IPC分类号： H01L27/105 , H01L21/8234 , H01L21/822 , H01L27/06
CPC分类号： H01L23/5252 , H01L27/1021 , H01L29/6609 , H01L2924/0002 , H01L2924/00
摘要： A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level. Other aspects are also described.
摘要翻译：单片三维存储器阵列通过一种方法形成，该方法包括通过在第一方向上形成多个沿第一方向延伸的多个第一基本上平行的导体形成第一存储器电平，ii）在第一导体上方形成第一柱，柱，其包括在垂直取向的二极管上方的第一导电层或层堆叠，在单个光刻步骤中形成的第一柱，iii）在第一柱上方沉积第一电介质层，以及iv）在第一栅极中蚀刻多个基本上平行的第一沟槽所述第一沟槽在第二方向上延伸，其中在所述蚀刻步骤之后，所述沟槽中的最低点高于所述第一导电层或层堆叠的最低点，其中所述第一导电层或所述层堆叠不包含电阻率开关金属氧化物或氮化物。该方法还包括在第一存储器级上方单片地形成第二存储器级。还描述了其他方面。

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