会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 66. 发明授权
    • Driver circuit
    • 驱动电路
    • US06175252B1
    • 2001-01-16
    • US09304270
    • 1999-05-06
    • Takashi Yamada
    • Takashi Yamada
    • H03K190175
    • H03K17/167
    • There is provided a driver circuit which does not require a large driving current, even when a logic circuit having a large capacity component is connected as the load. When the input voltage level is “H”, the first driving means inserted between the source and the load is maintained at the on state and it is turned off when it is detected by the first detecting means that the voltage level of the load exceeds the first voltage level. When the input voltage level is “L”, the second driving means inserted between the ground and the load is maintained at the on state and it is turned off when it is detected by the second detecting means that the voltage level of the load is below the second voltage level. The above mentioned first voltage level is higher than the logic threshold of the logic gate for receiving signals from the driver circuit, and the above mentioned second voltage level is lower than the logic threshold of the logic gate for receiving signals from the driver circuit.
    • 提供了不需要大的驱动电流的驱动电路,即使具有大容量分量的逻辑电路作为负载被连接。当输入电压电平为“H”时,第一驱动装置插入在源和 负载保持在接通状态,并且当第一检测装置检测到负载的电压电平超过第一电压电平时它被关断。 当输入电压电平为“L”时,插入接地和负载之间的第二驱动装置保持在接通状态,并且当第二检测装置检测到负载的电压电平低于 第二电压电平。 上述第一电压电平高于用于从驱动器电路接收信号的逻辑门的逻辑门限,并且上述第二电压电平低于用于从驱动器电路接收信号的逻辑门的逻辑门限。
    • 67. 发明授权
    • Semiconductor static random access memory device with low power
consumption in a write operation
    • 半导体静态随机存取存储器件在写操作中具有低功耗
    • US6147898A
    • 2000-11-14
    • US263089
    • 1999-03-08
    • Takashi Yamada
    • Takashi Yamada
    • G11C11/412G11C11/419G11C11/00
    • G11C11/419
    • There is disclosed an SRAM including a number of memory cells located in the form of a matrix. When data "0" is written to a memory cell 100, a precharge signal PC is brought to a high level so that a bit line D0 is brought into an electrically floating condition. A corresponding power switch 30 is turned off so that a pseudo-ground line SS0 is brought to an electrically floating condition. A corresponding equalizing transistor 20L is turned on so that the bit line having a power supply voltage Vdd as an initial potential and the pseudo-ground line SS0 having a ground voltage Vss as an initial potential are electrically connected to each other, so that the potential of the pseudo-ground line SS0 is elevated to a potential Veq which is determined by a ratio in capacitance of the bit line and the pseudo-ground line. As a result, the data holding capability of the memory cell 100 is lowered, and therefore, when a corresponding word line is pulled up, a latch in the memory cell 100 is quickly inverted, so that the writing operation is completed at a high speed. After the writing operation, the potential of the bit line D0 is returned to the initial potential Vdd. In this operation, since the potential of the bit line D0 was lowered only to the potential Veq, the potential of the bit line D0 is returned to the initial potential Vdd quickly with a reduced power consumption.
    • 公开了包括以矩阵形式定位的多个存储单元的SRAM。 当将数据“0”写入存储单元100时,使预充电信号PC达到高电平,使得位线D0进入电浮动状态。 相应的电源开关30被关闭,使得伪地线SS0变为电浮动状态。 相应的均衡晶体管20L导通,使得具有作为初始电位的电源电压Vdd的位线和具有接地电压Vss作为初始电位的伪地线SS0彼此电连接,使得电位 将伪地线SS0提高到由位线和伪地线的电容比确定的电位Veq。 结果,存储单元100的数据保持能力降低,因此当对应的字线被上拉时,存储单元100中的锁存器被快速反转,使得写入操作以高速完成 。 在写入操作之后,位线D0的电位返回到初始电位Vdd。 在该操作中,由于位线D0的电位仅降低到电位Veq,所以位线D0的电位以降低的功耗快速恢复到初始电位Vdd。
    • 68. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US6075397A
    • 2000-06-13
    • US178829
    • 1998-10-26
    • Takashi Yamada
    • Takashi Yamada
    • H01L27/04G11C11/417G11C11/419H01L21/822H03K5/135H03K17/30H03L7/06H03H11/26
    • G11C11/419G11C11/417H03K5/135
    • The present invention provides an technique for compensating a operation speed variation based on a principle that a circuit operation speed is adjusted by reflecting a delay time of an internal circuit itself that is an object of the operation speed fluctuation compensation.An internal circuit (1 in FIG. 1) has a critical path with an output terminal pair that outputs the identical logical values till its each operation is finished, and data in a complementary signal format as soon as its each operation is finished. A logical gate (2 in FIG. 1) can detect its operation end by sensing the signal transition into a complementary signal format at the output terminal pair of the internal circuit.
    • 本发明提供了一种基于通过反映作为操作速度波动补偿的对象的内部电路本身的延迟时间来调整电路操作速度的原理来补偿操作速度变化的技术。 内部电路(图1中的1)具有输出端子对的关键路径,其输出相同的逻辑值,直到其每个操作完成,并且一旦其每个操作完成就以互补信号格式的数据。 逻辑门(图1中的2)可以通过感测在内部电路的输出端子对处的信号转换为互补信号格式来检测其操作结束。
    • 69. 发明授权
    • Capillary electrophoresis apparatus
    • 毛细管电泳仪
    • US6048444A
    • 2000-04-11
    • US979542
    • 1997-11-26
    • Satoshi TakahashiHideki KambaraTakashi Yamada
    • Satoshi TakahashiHideki KambaraTakashi Yamada
    • G01N27/447G01N27/26
    • G01N27/44782G01N27/44721
    • A capillary electrophoresis apparatus of the invention has: a plurality of capillaries which are filled with a migration medium and have first ends into which samples are injected and second ends in which components included in the samples are eluted; a sheath flow cell in which the second ends are arranged in a straight line at first predetermined intervals and are terminated and a sheath flow is formed; a buffer solution vessel for housing a buffer solution flowing in the sheath flow cell; a drain vessel housing the buffer solution flowed from the sheath flow cell; an optical system emitting laser light to a part near the second ends; and a fluorescent detection system for detecting fluorescent light generated from fluorophore labelling the components included in the sample eluted near the second ends by the emission of laser light, wherein the buffer solution flows from the lower part to the upper part of the sheath flow cell, thereby forming a sheath flow in the sheath flow cell.
    • 本发明的毛细管电泳装置具有:填充有迁移介质的多个毛细管,其具有注入样品的第一端和样品中包含的成分被洗脱的第二端; 鞘流池,其中第二端以第一预定间隔以直线布置并且终止并形成鞘流; 用于容纳在鞘流池中流动的缓冲溶液的缓冲溶液容器; 容纳从鞘流池流出的缓冲溶液的排水管; 将激光发射到靠近第二端的部分的光学系统; 以及荧光检测系统,用于检测由荧光团产生的荧光,其中通过发射激光来标记在第二端附近洗脱的样品中包含的成分,其中缓冲溶液从鞘流动池的下部流向上部, 从而在鞘流动池中形成鞘流。