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61. 发明授权

US06185149B2 Semiconductor integrated circuit memory 有权
标题翻译：半导体集成电路存储器
公开(公告)号：US06185149B2
公开(公告)日：2001-02-06
申请号：US09340147
申请日：1999-06-28
申请人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
发明人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.
摘要翻译：半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块长度。从上述一个或多个存储单元块读取数据。

62. 发明授权

US5986960A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5986960A
公开(公告)日：1999-11-16
申请号：US910899
申请日：1997-08-13
申请人： Shinya Fujioka , Atsushi Hatakeyama
发明人： Shinya Fujioka , Atsushi Hatakeyama
IPC分类号： G11C11/413 , G11C5/14 , G11C8/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C11/409 , H01L27/10 , G11C7/00
CPC分类号： G11C5/147 , G11C11/4082 , G11C11/4087 , G11C8/10 , Y10T307/826
摘要： A semiconductor integrated circuit having a DRAM, or the like, includes a memory cell block containing a plurality of memory cells, and a core circuit portion for selecting and activating a specified memory cell inside the memory cell block, and is constituted so that a step-up voltage is applied to the core circuit portion at the time of an activated state. The semiconductor integrated circuit further includes a step-up voltage lowering unit for lowering the step-up voltage by a predetermined value and a unit for selectively supplying the step-up voltage and an output voltage of the step-up voltage lowering unit to the core circuit portion.
摘要翻译：具有DRAM等的半导体集成电路包括包含多个存储单元的存储单元块和用于选择和激活存储单元块内的指定存储单元的核心电路部分，并且构成为步骤在激活状态时，向核心电路部分施加电压。半导体集成电路还包括用于将升压电压降低预定值的升压降压单元和用于选择性地将升压电压和升压降压单元的输出电压提供给芯的单元电路部分

63. 发明授权

US5742554A Volatile memory device and method of refreshing same 失效
标题翻译：易失性存储器件及刷新方法
公开(公告)号：US5742554A
公开(公告)日：1998-04-21
申请号：US685859
申请日：1996-07-24
申请人： Shinya Fujioka
发明人： Shinya Fujioka
IPC分类号： G11C11/406 , G11C11/407 , G11C7/00 , G11C8/00
CPC分类号： G11C11/406
摘要： A volatile memory device or a refreshing method for refreshing information stored in a plurality of memory cells, comprises: a plurality of banks each having a plurality of cell array blocks each of which have a plurality of memory cells and a decoder portion for selecting the memory cells; an address buffer being supplied with an address signal; and a plurality of predecoders associated respectively with the banks, for being supplied with an output signal from the address buffer and supplying predecoded signals to the associated banks. When the volatile memory device is refreshed, the predecoder associated with one of the banks which is selected is activated, and a plurality of cell array blocks in the selected bank are simultaneously selected, and the predecoders associated with the banks which are unselected are inactivated. According to the present invention, the high speed refresh and low power consumption can be realized.
摘要翻译：一种用于刷新存储在多个存储器单元中的信息的易失性存储器件或刷新方法，包括：多个存储体，每个存储体具有多个单元阵列块，每个单元阵列块具有多个存储单元;以及解码器部分，用于选择存储器细胞; 地址缓冲器被提供有地址信号; 以及分别与存储体相关联的多个预解码器，用于从地址缓冲器提供输出信号，并向相关联的存储体提供预解码信号。当易失性存储器件被刷新时，与所选择的一个存储体相关联的预解码器被激活，并且同时选择所选存储体中的多个单元阵列块，并且与未被选择的存储体相关联的预解码器被去激活。根据本发明，可以实现高速刷新和低功耗。

64. 发明申请

US20120087662A1 PASSIVE OPTICAL NETWORK AND SUBSCRIBER LINE TERMINAL 审中-公开
标题翻译：被动光网络和订户线终端
公开(公告)号：US20120087662A1
公开(公告)日：2012-04-12
申请号：US13240634
申请日：2011-09-22
申请人： Katsuyoshi Suzuki , Masao Niibe , Shinya Fujioka , Masahiko Mizutani
发明人： Katsuyoshi Suzuki , Masao Niibe , Shinya Fujioka , Masahiko Mizutani
IPC分类号： H04J14/00
CPC分类号： H04J14/0282 , H04J3/1694 , H04J14/0247 , H04J14/0252 , H04J14/0256 , H04J14/026 , H04Q11/0067 , H04Q2011/0079
摘要： The OLT manages information of optical intensity and communication bit rate receivable by each ONU, and transmits a signal at suitable optical intensity and a bit rate. The OLT decides a signal transmission plan for each ONU according to a status of accumulated information waiting to be transmitted in the OLT's own device buffer, and inserts the signal transmission plan in a header or payload of a downlink frame, thereby notifying the ONUs of the information prior to transmitting accumulated information (primary signal). The ONU recognizes the signal transmission plan of the OLT according to the time information in a downlink intensity map, receives only a signal having the optical intensity and bit rate suitable for the ONU's own device, and blocks other signals.
摘要翻译： OLT管理每个ONU可接收的光强度和通信比特率信息，并以适当的光强度和比特率发送信号。 OLT根据等待在OLT自己的设备缓冲区中发送的累计信息的状态，决定每个ONU的信号传输计划，并将信号传输计划插入到下行链路帧的报头或有效载荷中，从而通知ONU的发送累积信息之前的信息（主信号）。 ONU根据下行链路强度图中的时间信息识别OLT的信号传输计划，仅接收具有适合于ONU本身设备的光强度和比特率的信号，并阻止其他信号。

65. 发明授权

US08149644B2 Memory system and method that changes voltage and frequency 有权
标题翻译：改变电压和频率的存储器系统和方法
公开(公告)号：US08149644B2
公开(公告)日：2012-04-03
申请号：US12257799
申请日：2008-10-24
申请人： Shinya Fujioka , Yasuyuki Eguchi
发明人： Shinya Fujioka , Yasuyuki Eguchi
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C11/4074 , G11C2207/2227
摘要： The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit coupled to the internal circuit and operates according to a second power supply voltage, a first control unit that includes a control input/output circuit, coupled to the memory input/output circuit and operates according to the second power supply voltage, a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal, a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal, and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.
摘要翻译：存储器系统包括具有根据第一电源电压工作的内部电路的半导体存储器和耦合到内部电路并根据第二电源电压进行操作的存储器输入/输出电路，第一控制单元，包括耦合到存储器输入/输出电路并根据第二电源电压进行操作的控制输入/输出电路，产生第二电源电压并根据电压调节信号改变第二电源电压的电压产生单元时钟发生单元，其产生时钟信号并根据时钟调整信号改变时钟信号的频率;以及第二控制单元，其根据半导体存储器的访问状态产生电压调整信号和时钟调整信号由第一控制单元。

66. 发明申请

US20050276134A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20050276134A1
公开(公告)日：2005-12-15
申请号：US11024734
申请日：2004-12-30
申请人： Kaoru Mori , Shinya Fujioka
发明人： Kaoru Mori , Shinya Fujioka
IPC分类号： G11C11/409 , G11C5/14 , G11C7/00 , G11C11/406 , G11C11/4091 , G11C11/4094 , G11C29/02
CPC分类号： G11C11/406 , G11C5/147 , G11C11/4094 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C2029/5006 , G11C2211/4065 , G11C2211/4067
摘要： A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.
摘要翻译：提供了一种存储器件，其具有：用于存储数据的存储器单元; 一个字线选择存储单元; 可选择的存储单元的位线; 预充电电源，用于向位线提供预充电电压; 预充电电路，用于将预充电电源连接到或从所述位线断开; 以及电流限制元件，用于根据操作状态至少两步地控制在预充电电源和位线之间流动的电流的大小。

67. 发明授权

US06971052B2 Semiconductor integrated circuit and method for testing the same 失效
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US06971052B2
公开(公告)日：2005-11-29
申请号：US10255671
申请日：2002-09-27
申请人： Hiroyoshi Tsuboi , Shinya Fujioka
发明人： Hiroyoshi Tsuboi , Shinya Fujioka
IPC分类号： G01R31/28 , G01R31/3181 , G01R31/3185 , G11C29/00 , G11C29/46 , H01L21/822 , H01L27/04
CPC分类号： G11C29/46 , G01R31/3181
摘要： When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times. The number of times of the test command supplied to start or terminate the second and subsequent tests can be less than that of the first test. Accordingly, the time of the second and subsequent tests can be shortened. Since the first test is started only when the test command is received n times, the test is not started accidentally due to noise or the like in normal operation. Namely, the test time can be shortened without decreasing the operation reliability of an integrated circuit. Particularly, when a plurality of tests is executed successively, great benefit can be obtained.
摘要翻译：当接收到n次测试命令时，开始多个测试中的任何一个。在第一次测试开始之后，每次接收到测试命令的预定次数小于n次时，任何一个测试都被启动或终止。提供用于开始或终止第二次和后续测试的测试命令的次数可以小于第一次测试的次数。因此，可以缩短第二次和随后的测试的时间。由于仅在接收到n次测试命令时开始第一次测试，因此在正常操作中由于噪音等原因而不会意外启动测试。也就是说，可以缩短测试时间而不降低集成电路的操作可靠性。特别地，当连续执行多个测试时，可以获得很大的益处。

68. 发明授权

US06473347B2 Semiconductor device having memory with effective precharging scheme 有权
标题翻译：具有具有有效预充电方案的存储器的半导体器件
公开(公告)号：US06473347B2
公开(公告)日：2002-10-29
申请号：US09929354
申请日：2001-08-15
申请人： Katsuhiro Mori , Shinya Fujioka , Akihiro Funya
发明人： Katsuhiro Mori , Shinya Fujioka , Akihiro Funya
IPC分类号： G11C7100
CPC分类号： G11C29/50 , G11C8/08 , G11C11/401
摘要： A semiconductor device includes a plurality of word lines selectable in a predetermined mode, and a circuit that precharges the plurality of word lines selected in the predetermined mode in a time division manner.
摘要翻译：半导体器件包括以预定模式可选择的多个字线，以及以时分方式对以预定模式选择的多个字线进行预充电的电路。

69. 发明授权

US06324111B1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06324111B1
公开(公告)日：2001-11-27
申请号：US09561217
申请日：2000-04-28
申请人： Yasuharu Sato , Shinya Fujioka
发明人： Yasuharu Sato , Shinya Fujioka
IPC分类号： G11C702
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/065
摘要： A semiconductor memory includes p-type MOS transistors (11) dispersed in one-to-one correspondence with sense amplifiers (4−1-4−n) to activate their corresponding sense amplifiers, and a p-type MOS transistor (12) to activate the sense amplifiers (4−1-4−n). After the p-type MOS transistors (11) are overdriven by an external voltage (VCC) higher than a memory stored voltage, the p-type MOS transistor (12) is driven by an internal step-down voltage (VII) that is the memory stored voltage. This increases the driving capability per sense amplifier in comparison with a conventional method and further increases the speed of sense operation in comparison with a simple overdriving method.
摘要翻译：半导体存储器包括与读出放大器（4-1-4-n）一一对应地分散以激活其对应的读出放大器的p型MOS晶体管（11），以及p型MOS晶体管（12），激活读出放大器（4-1-4-n）。在p型MOS晶体管（11）被高于存储器存储电压的外部电压（VCC）驱动之后，p型MOS晶体管（12）由内部降压电压（VII）驱动，存储电压。与传统方法相比，这增加了每个读出放大器的驱动能力，并且与简单的过驱动方法相比进一步增加了感测操作的速度。

70. 发明授权

US06239631B1 Integrated circuit device with input buffer capable of correspondence with highspeed clock 有权
标题翻译：具有与高速时钟对应的输入缓冲器的集成电路器件
公开(公告)号：US06239631B1
公开(公告)日：2001-05-29
申请号：US09377104
申请日：1999-08-19
申请人： Shinya Fujioka , Hiroyoshi Tomita
发明人： Shinya Fujioka , Hiroyoshi Tomita
IPC分类号： H03L700
CPC分类号： G11C7/1093 , G06F5/06 , G11C7/1087 , G11C7/222 , H03L7/00
摘要： One aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another. According to the present invention, the operation of input buffers of a plurality of sets are synchronized with internal clocks of a slower speed than a supplied clock, thus enabling the reliable receive of input signals.
摘要翻译：本发明的一个方面的特征在于，输入缓冲电路构成2组或相对于1个输入信号的多组，一对互补的内部时钟或多个内部时钟通过分频产生集成电路器件内的提供的时钟和输入信号可以与一对互补时钟同步地接收和锁存，或者根据两组或多组的输入缓冲器与多个时钟同步地被接收和锁存。 2组或多组的输入缓冲器的输出由组合电路组合，并在内部提供。为内部产生的内部时钟设置一个H电平或一个L电平周期，使得各种输入缓冲器的输出不会相互竞争。根据本发明，多个组的输入缓冲器的操作与比所提供的时钟慢的内部时钟同步，因此能够可靠地接收输入信号。

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