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1. 发明授权

US08149644B2 Memory system and method that changes voltage and frequency 有权
标题翻译：改变电压和频率的存储器系统和方法
公开(公告)号：US08149644B2
公开(公告)日：2012-04-03
申请号：US12257799
申请日：2008-10-24
申请人： Shinya Fujioka , Yasuyuki Eguchi
发明人： Shinya Fujioka , Yasuyuki Eguchi
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C11/4074 , G11C2207/2227
摘要： The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit coupled to the internal circuit and operates according to a second power supply voltage, a first control unit that includes a control input/output circuit, coupled to the memory input/output circuit and operates according to the second power supply voltage, a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal, a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal, and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.
摘要翻译：存储器系统包括具有根据第一电源电压工作的内部电路的半导体存储器和耦合到内部电路并根据第二电源电压进行操作的存储器输入/输出电路，第一控制单元，包括耦合到存储器输入/输出电路并根据第二电源电压进行操作的控制输入/输出电路，产生第二电源电压并根据电压调节信号改变第二电源电压的电压产生单元时钟发生单元，其产生时钟信号并根据时钟调整信号改变时钟信号的频率;以及第二控制单元，其根据半导体存储器的访问状态产生电压调整信号和时钟调整信号由第一控制单元。

2. 发明申请

US20090154257A1 MEMORY SYSTEM AND CONTROL METHOD FOR MEMORY 有权
标题翻译：用于存储器的存储器系统和控制方法
公开(公告)号：US20090154257A1
公开(公告)日：2009-06-18
申请号：US12257799
申请日：2008-10-24
申请人： Shinya FUJIOKA , Yasuyuki Eguchi
发明人： Shinya FUJIOKA , Yasuyuki Eguchi
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C11/4074 , G11C2207/2227
摘要： The memory system comprises: a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage; a first control unit that includes a control input/output circuit, which is coupled to the memory input/output circuit and operates according to the second power supply voltage; a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal; a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal; and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.
摘要翻译：所述存储器系统包括：半导体存储器，其包括根据第一电源电压工作的内部电路和存储器输入/输出电路，所述存储器输入/输出电路耦合到所述内部电路并根据第二电源电压进行操作; 第一控制单元，其包括控制输入/输出电路，其耦合到所述存储器输入/输出电路并根据所述第二电源电压进行操作; 电压产生单元，其产生第二电源电压并根据电压调节信号改变第二电源电压; 时钟发生单元，其产生时钟信号并根据时钟调整信号改变时钟信号的频率; 以及第二控制单元，其根据第一控制单元的半导体存储器的访问状态生成电压调整信号和时钟调整信号。

3. 发明授权

US07746718B2 Semiconductor memory, operating method of semiconductor memory, memory controller, and system 有权
标题翻译：半导体存储器，半导体存储器的操作方法，存储器控制器和系统
公开(公告)号：US07746718B2
公开(公告)日：2010-06-29
申请号：US11998428
申请日：2007-11-30
申请人： Yasuyuki Eguchi , Shinya Fujioka , Yoshiaki Okuyama
发明人： Yasuyuki Eguchi , Shinya Fujioka , Yoshiaki Okuyama
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C8/12 , G11C11/40622
摘要： A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.
摘要翻译：刷新寄存器存储指示将被禁用刷新操作的存储器块的禁止块信息。刷新控制电路周期性地执行除了与禁用块信息相对应的存储块之外的存储器块的刷新操作。在对存储器块之一的访问周期期间，寄存器控制电路根据外部输入将该禁止块信息写入刷新寄存器。因此，为了重写刷新寄存器，不需要对访问周期使用附加的操作周期。由于不需要插入额外的操作周期，因此可以改变要刷新的存储器区域，而不会降低访问周期的有效效率。结果，可以降低功耗。

4. 发明申请

US20080144417A1 Semiconductor memory, operating method of semiconductor memory, memory controller, and system 有权
标题翻译：半导体存储器，半导体存储器的操作方法，存储器控制器和系统
公开(公告)号：US20080144417A1
公开(公告)日：2008-06-19
申请号：US11998428
申请日：2007-11-30
申请人： Yasuyuki Eguchi , Shinya Fujioka , Yoshiaki Okuyama
发明人： Yasuyuki Eguchi , Shinya Fujioka , Yoshiaki Okuyama
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C8/12 , G11C11/40622
摘要： A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.
摘要翻译：刷新寄存器存储指示将被禁用刷新操作的存储器块的禁止块信息。刷新控制电路周期性地执行除了与禁用块信息相对应的存储块之外的存储器块的刷新操作。在对存储器块之一的访问周期期间，寄存器控制电路根据外部输入将该禁止块信息写入刷新寄存器。因此，为了重写刷新寄存器，不需要对访问周期使用附加的操作周期。由于不需要插入额外的操作周期，因此可以改变要刷新的存储区域，而不会降低访问周期的有效效率。结果，可以降低功耗。

5. 发明授权

US07242631B2 Semiconductor memory device and information processing system 有权
标题翻译：半导体存储器件和信息处理系统
公开(公告)号：US07242631B2
公开(公告)日：2007-07-10
申请号：US11236739
申请日：2005-09-28
申请人： Shinya Fujioka , Yasuyuki Eguchi , Atsushi Sukeno , Koutoku Sato
发明人： Shinya Fujioka , Yasuyuki Eguchi , Atsushi Sukeno , Koutoku Sato
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C11/406 , G11C11/40611 , G11C11/40615
摘要： A refresh operation at a memory cell array for keeping data stored in memory cells is enabled to be switched whether to be executed based on an external refresh request inputted from external or an internal refresh request generated internally by a refresh control unit, and therefore, when the refresh operation is executed based on the external refresh request, it becomes possible to execute an access operation for the memory cell array in accordance with an access request from external only with a necessary time for executing the operation in accordance with the access request without including a necessary time for executing the refresh operation.
摘要翻译：存储单元阵列中用于保存存储在存储单元中的数据的刷新操作能够基于从外部输入的外部刷新请求或由刷新控制单元内部生成的内部刷新请求进行切换，因此，当基于外部刷新请求执行刷新操作，可以根据来自外部的访问请求执行对存储单元阵列的访问操作，只需要具有根据访问请求执行操作所需的时间，而不包括执行刷新操作的必要时间。

6. 发明申请

US20060274591A1 Semiconductor memory device and information processing system 有权
标题翻译：半导体存储器件和信息处理系统
公开(公告)号：US20060274591A1
公开(公告)日：2006-12-07
申请号：US11236739
申请日：2005-09-28
申请人： Shinya Fujioka , Yasuyuki Eguchi , Atsushi Sukeno , Koutoku Sato
发明人： Shinya Fujioka , Yasuyuki Eguchi , Atsushi Sukeno , Koutoku Sato
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C11/406 , G11C11/40611 , G11C11/40615
摘要： A refresh operation at a memory cell array for keeping data stored in memory cells is enabled to be switched whether to be executed based on an external refresh request inputted from external or an internal refresh request generated internally by a refresh control unit, and therefore, when the refresh operation is executed based on the external refresh request, it becomes possible to execute an access operation for the memory cell array in accordance with an access request from external only with a necessary time for executing the operation in accordance with the access request without including a necessary time for executing the refresh operation.
摘要翻译：存储单元阵列中用于保存存储在存储单元中的数据的刷新操作能够基于从外部输入的外部刷新请求或由刷新控制单元内部生成的内部刷新请求进行切换，因此，当基于外部刷新请求执行刷新操作，可以根据来自外部的访问请求执行对存储单元阵列的访问操作，只需要具有根据访问请求执行操作所需的时间，而不包括执行刷新操作的必要时间。

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