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61. 发明授权

US06780779B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06780779B2
公开(公告)日：2004-08-24
申请号：US10222855
申请日：2002-08-19
申请人： Tetsuya Ueda , Eiji Tamaoka , Nobuo Aoi
发明人： Tetsuya Ueda , Eiji Tamaoka , Nobuo Aoi
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31144 , H01L21/76801 , H01L21/76811 , H01L21/76837 , H01L21/76885 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.
摘要翻译：在形成在半导体衬底上的绝缘膜上依次沉积第一金属膜和第一氧化硅膜之后，通过使用第一抗蚀剂图案作为掩模进行蚀刻，从而形成具有开口的第一层间绝缘膜第一氧化硅膜和第一金属互连从第一金属膜。在第一层间绝缘膜的开口部填充有机膜的第三层间绝缘膜，使用硬掩模对第一层间绝缘膜进行蚀刻。然后将第二金属膜填充在第二层间绝缘膜的空间中，以形成第二金属互连。

62. 发明授权

US06545361B2 Semiconductor device having multilevel interconnection structure and method for fabricating the same 有权
标题翻译：具有多层互连结构的半导体器件及其制造方法
公开(公告)号：US06545361B2
公开(公告)日：2003-04-08
申请号：US09835169
申请日：2001-04-16
申请人： Tetsuya Ueda , Eiji Tamaoka , Nobuo Aoi
发明人： Tetsuya Ueda , Eiji Tamaoka , Nobuo Aoi
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/7682 , H01L21/76838 , H01L21/76885 , H01L23/5222 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrate so as to cover the interconnecting metal and the first interconnect layer; planarizing the second interlevel dielectric film, thereby exposing at least part of the interconnecting metal; and forming a second interconnect layer to be electrically connected to an upper part of the interconnecting metal.
摘要翻译：根据本发明的制造具有多层互连结构的半导体器件的方法包括以下步骤：用绝缘膜覆盖衬底的表面; 在绝缘膜上沉积导电膜; 在导电膜上形成第一层间电介质膜; 在所述第一层间绝缘膜中形成层间接触孔，以到达所述导电膜; 用互连金属填充层间接触孔; 在所述第一层间绝缘膜上形成限定第一互连层图案的掩模层，以便覆盖所述互连金属的至少一部分; 通过使用掩模层作为掩模蚀刻第一层间电介质膜，并且使用掩模层和互连金属作为掩模蚀刻导电膜，从导电膜形成第一互连层; 去除掩蔽层; 在所述衬底上沉积第二层间电介质膜以便覆盖所述互连金属和所述第一互连层; 平面化第二层间电介质膜，从而暴露至少部分互连金属; 以及形成与所述互连金属的上部电连接的第二互连层。

63. 发明授权

US06495451B2 Method of forming interconnect 有权
标题翻译：形成互连的方法
公开(公告)号：US06495451B2
公开(公告)日：2002-12-17
申请号：US09753675
申请日：2001-01-04
申请人： Tsukasa Hattori , Takashi Matsuda , Hiroshi Masuda , Tetsuya Ueda
发明人： Tsukasa Hattori , Takashi Matsuda , Hiroshi Masuda , Tetsuya Ueda
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/31144 , H01L21/76804 , H01L21/76807 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An interconnect forming method includes the steps of: a) forming a through hole in an insulating film over a substrate; b) depositing a photosensitive masking material over the insulating film as well as inside the hole; c) patterning the material, thereby forming a mask pattern, which has an opening located over the hole and is used to define a trench; d) etching the insulating film to a predetermined depth using the mask pattern, thereby defining a trench pattern, linked to the hole, in an upper part of the insulating film; e) filling in the hole and the trench pattern with a conductive material; and f) before the trench pattern is defined, defining the mask pattern so that no remaining part of the material, which has been filled in the hole, will reach a level higher than the bottom of the trench pattern.
摘要翻译：互连形成方法包括以下步骤：a）在衬底上形成绝缘膜中的通孔; b）在绝缘膜上以及孔内沉积感光掩模材料; c）图案化材料，从而形成掩模图案，其具有位于孔上方的开口并用于限定沟槽; d）使用掩模图案将绝缘膜蚀刻到预定深度，从而在绝缘膜的上部限定连接到孔的沟槽图案; e）用导电材料填充孔和沟槽图案; 以及f）在限定沟槽图案之前，限定掩模图案，使得已经填充在孔中的材料的剩余部分将不会达到比沟槽图案的底部高的水平。

64. 发明授权

US5986313A Semiconductor device comprising MISFETS and method of manufacturing the same 失效
标题翻译：包括MISFET的半导体器件及其制造方法
公开(公告)号：US5986313A
公开(公告)日：1999-11-16
申请号：US988776
申请日：1997-12-11
申请人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
发明人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/417 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/823475 , H01L29/41775 , H01L29/41783 , H01L29/66545
摘要： There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for ccntact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.
摘要翻译：形成围绕半导体衬底的有源区的隔离。分别在有源区和隔离层上形成栅电极和两侧栅极互连。在栅极电极和栅极互连之间设置两个第一空间，每个空间的宽度小于指定值，第二空间的宽度大于指定值并插入在两个第一间隙之间。在通过在衬底上沉积绝缘膜来形成栅电极的两个侧面上的侧壁和栅极互连时，第一间隙被绝缘膜掩埋。然后，将金属膜沉积在基板上，然后进行化学机械抛光，直到栅极，栅极互连和侧壁变得暴露。通过该处理，通过自对准来形成用于与有源区域成反射的源极/漏极区域的引出电极，而引出的电极通过侧壁与栅电极和栅极互连绝缘。

65. 发明授权

US5733812A Semiconductor device with a field-effect transistor having a lower resistance impurity diffusion layer, and method of manufacturing the same 失效
标题翻译：具有具有较低电阻杂质扩散层的场效应晶体管的半导体器件及其制造方法
公开(公告)号：US5733812A
公开(公告)日：1998-03-31
申请号：US571131
申请日：1995-12-12
申请人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
发明人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/417 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/823475 , H01L29/41775 , H01L29/41783 , H01L29/66545
摘要： There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for contact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.
摘要翻译：形成围绕半导体衬底的有源区的隔离。分别在有源区和隔离层上形成栅电极和两侧栅极互连。在栅极电极和栅极互连之间设置两个第一空间，每个空间的宽度小于指定值，第二空间的宽度大于指定值并插入在两个第一间隙之间。在通过在衬底上沉积绝缘膜来形成栅电极的两个侧面上的侧壁和栅极互连时，第一间隙被绝缘膜掩埋。然后，将金属膜沉积在基板上，然后进行化学机械抛光，直到栅极，栅极互连和侧壁变得暴露。通过该处理，通过自对准形成来自用于与有源区接触的源极/漏极区域的引出电极，而引出的电极通过侧壁与栅电极和栅极互连绝缘。

66. 发明授权

US5545919A Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5545919A
公开(公告)日：1996-08-13
申请号：US497756
申请日：1995-07-03
申请人： Satoshi Ueda , Tetsuya Ueda , Atsuhiro Yamano , Kousaku Yano
发明人： Satoshi Ueda , Tetsuya Ueda , Atsuhiro Yamano , Kousaku Yano
IPC分类号： H01L21/31 , H01L21/316 , H01L21/318 , H01L23/31 , H01L23/52 , H01L23/532 , H01L23/58
CPC分类号： H01L23/3171 , H01L23/5329 , H01L2924/0002
摘要： Metal wires are formed side by side over a semiconductor substrate, with an interlayer insulating film interposed between the metal interconnections and the semiconductor substrate. The metal interconnections are covered with a passivation film composed of a lower silicon oxide film and an upper silicon nitride film. The silicon oxide film is deposited so that the maximum thickness of the portions of the silicon oxide film on the side faces of the metal interconnections is less than half of the minimum space between the metal interconnections. The silicon nitride film is deposited so as to be interposed between the portions of the silicon oxide film on the side faces of the adjacent metal interconnections.
摘要翻译：金属线并排地形成在半导体衬底上，层间绝缘膜介于金属互连和半导体衬底之间。金属互连用由下部氧化硅膜和上部氮化硅膜构成的钝化膜覆盖。沉积氧化硅膜，使得金属互连侧面上的氧化硅膜的部分的最大厚度小于金属互连之间的最小空间的一半。沉积氮化硅膜以便在相邻的金属互连的侧面上介于氧化硅膜的部分之间。

67. 发明授权

US5518513A Dust removing apparatus 失效
标题翻译：除尘装置
公开(公告)号：US5518513A
公开(公告)日：1996-05-21
申请号：US307056
申请日：1994-09-16
申请人： Atsumasa Iwanaga , Kiyoshi Nagashima , Tetsuya Ueda , Hisataka Urakata , Tetsuya Fujino
发明人： Atsumasa Iwanaga , Kiyoshi Nagashima , Tetsuya Ueda , Hisataka Urakata , Tetsuya Fujino
IPC分类号： B01D46/00 , B01D46/24 , B01D46/42
CPC分类号： B01D46/2407 , B01D46/002 , B01D46/0049 , B01D46/0067 , B01D46/2418
摘要： A dust removing apparatus suppresses pressure and temperature variations of cleaned gas to facilitate the removal of dust. A clean gas chamber delimited by a plurality of porous ceramic tubular filter elements is divided in two by a partition wall. The respective chambers are connected through discrete outlet pipes to a clean gas main pipe, and backwashing devices are provided in the respective outlet pipes. Furthermore, a porous ceramics filter element is provided on a bottom partition plate so that the gas flow velocity in the tubular filter elements can be insured to prevent dust from adhering thereto.
摘要翻译：除尘装置抑制净化气体的压力和温度变化，以便除尘。由多个多孔陶瓷管状过滤器元件限定的清洁气体室由分隔壁分成两部分。各个室通过离散出口管连接到清洁气体主管，并且反洗装置设置在相应的出口管中。此外，在底部隔板上设置多孔陶瓷过滤元件，使得可以保证管状过滤元件中的气体流速，以防止灰尘附着在其上。

68. 发明授权

US5385867A Method for forming a multi-layer metallic wiring structure 失效
标题翻译：用于形成多层金属布线结构的方法
公开(公告)号：US5385867A
公开(公告)日：1995-01-31
申请号：US216968
申请日：1994-03-24
申请人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
发明人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/283 , H01L21/31
CPC分类号： H01L21/76847 , H01L21/76844 , H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L2924/0002 , Y10S438/948
摘要： After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion. After accumulating an inter-layer insulating film layer on the first Al--Si--Cu film layer, etchback is applied on this inter-layer insulating film layer until the top of the tall metallic film portion is bared. Then, the second-layer metallic wiring is formed on the inter-layer insulating film layer so that the second-layer metallic wiring is connected with the tall metallic film portion.
摘要翻译：在硅衬底上积累BPSG膜层之后，第一Al-Si-Cu膜层，W膜层和第二Al-Si-Cu膜层依次堆积在该BPSG膜层上。在第二Al-Si-Cu膜层上形成具有宽幅和窄宽图案部分的抗蚀剂图案。宽幅图形部分设置在与用于连接第一层金属布线和第二层金属布线的接触件相对应的位置处，而窄宽图案部分设置在与布线部分相对应的位置处第一层金属布线。在具有抗蚀剂图案的掩模的第二Al-Si-Cu膜层上施加第一蚀刻之后，在W膜层上施加第二蚀刻。此后，通过施加第三蚀刻，去除残留在第一层金属布线上的抗蚀剂图案，并将第一Al-Si-Cu膜层变形为高金属膜部分和短金属膜部分。在第一Al-Si-Cu膜层上积累层间绝缘膜层之后，在该层间绝缘膜层上施加回蚀，直到高金属膜部分的顶部露出。然后，在层间绝缘膜层上形成第二层金属布线，使得第二层金属布线与高金属膜部分连接。

69. 发明授权

US09115418B2 Method of recovering platinum group elements 有权
标题翻译：回收铂族元素的方法
公开(公告)号：US09115418B2
公开(公告)日：2015-08-25
申请号：US14004334
申请日：2012-03-07
申请人： Yuzuru Nakamura , Minoru Kawasaki , Katsunori Yamaguchi , Tetsuya Ueda , Keiko Ishizaki
发明人： Yuzuru Nakamura , Minoru Kawasaki , Katsunori Yamaguchi , Tetsuya Ueda , Keiko Ishizaki
IPC分类号： C22B11/02 , C22B11/00
CPC分类号： C22B11/02 , C22B11/021 , Y02P10/214
摘要： Provided is a method of unevenly distributing a specific element in a copper phase out of platinum group elements that exist in the copper phase, including further adding copper into a molten copper phase containing the platinum group elements including at least rhodium, thereby increasing a distribution ratio of rhodium in the molten copper phase.
摘要翻译：提供了一种从铜相中存在的铂族元素中不均匀地分布铜相中的特定元素的方法，包括进一步将铜添加到含有至少包含铑的铂族元素的熔融铜相中，从而增加分配比的铑在熔融铜相中。

70. 发明授权

US08502385B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08502385B2
公开(公告)日：2013-08-06
申请号：US13150593
申请日：2011-06-01
申请人： Seiji Oka , Tetsuya Ueda
发明人： Seiji Oka , Tetsuya Ueda
IPC分类号： H01L23/48 , H01L23/498
CPC分类号： H01L21/56 , H01L23/3121 , H01L23/49811 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/072 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/73265 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01322 , H01L2924/12041 , H01L2924/13055 , H01L2924/181 , H01L2924/30107 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A power semiconductor device has the power semiconductor elements having back surfaces bonded to wiring patterns and surface electrodes, cylindrical communication parts having bottom surfaces bonded on the surface electrodes of the power semiconductor elements and/or on the wiring patterns, a transfer mold resin having concave parts which expose the upper surfaces of the communication parts and cover the insulating layer, the wiring patterns, and the power semiconductor elements. External terminals have one ends inserted in the upper surfaces of the communication parts and the other ends guided upward, and at least one external terminal has, between both end parts, a bent area which is bent in an L shape and is embedded in the concave part of the transfer mold resin.
摘要翻译：功率半导体器件具有将背面接合到布线图案和表面电极的功率半导体元件，具有接合在功率半导体元件的表面电极上和/或布线图案上的底面的圆筒形连通部分，具有凹形露出通信部的上表面并覆盖绝缘层的部分，布线图案和功率半导体元件。外部端子的一端插入连通部的上表面，另一端被向上引导，并且至少一个外部端子在两端部之间具有弯曲的L形的弯曲区域并嵌入凹部部分转移模具树脂。

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